Conferences in DBLP

International Conference on Parallel Architectures and Compilation Techniques (PACT) (IEEEpact)
2008 (conf/IEEEpact/2008)

1. 
   GPU evolution: will graphics morph into compute? [Citation Graph (, )][DBLP]
   
   
2. 
   Outer-loop vectorization: revisited for short SIMD architectures. [Citation Graph (, )][DBLP]
   
   
3. 
   Redundancy elimination revisited. [Citation Graph (, )][DBLP]
   
   
4. 
   Exploiting loop-dependent stream reuse for stream processors. [Citation Graph (, )][DBLP]
   
   
5. 
   Feature selection and policy optimization for distributed instruction placement using reinforcement learning. [Citation Graph (, )][DBLP]
   
   
6. 
   Core cannibalization architecture: improving lifetime chip performance for multicore processors in the presence of hard faults. [Citation Graph (, )][DBLP]
   
   
7. 
   Pangaea: a tightly-coupled IA32 heterogeneous chip multiprocessor. [Citation Graph (, )][DBLP]
   
   
8. 
   Skewed redundancy. [Citation Graph (, )][DBLP]
   
   
9. 
   The PARSEC benchmark suite: characterization and architectural implications. [Citation Graph (, )][DBLP]
   
   
10. 
    Visualizing potential parallelism in sequential programs. [Citation Graph (, )][DBLP]
    
    
11. 
    Characterizing and modeling the behavior of context switch misses. [Citation Graph (, )][DBLP]
    
    
12. 
    MCAMP: communication optimization on massively parallel machines with hierarchical scratch-pad memory. [Citation Graph (, )][DBLP]
    
    
13. 
    Profiler and compiler assisted adaptive I/O prefetching for shared storage caches. [Citation Graph (, )][DBLP]
    
    
14. 
    Runtime optimization of vector operations on large scale SMP clusters. [Citation Graph (, )][DBLP]
    
    
15. 
    (How) can programmers conquer the multicore menace? [Citation Graph (, )][DBLP]
    
    
16. 
    Distributed cooperative caching. [Citation Graph (, )][DBLP]
    
    
17. 
    Scalable and reliable communication for hardware transactional memory. [Citation Graph (, )][DBLP]
    
    
18. 
    Improving support for locality and fine-grain sharing in chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
19. 
    Edge-centric modulo scheduling for coarse-grained reconfigurable architectures. [Citation Graph (, )][DBLP]
    
    
20. 
    Multi-optimization power management for chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
21. 
    Multitasking workload scheduling on flexible-core chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
22. 
    Leveraging on-chip networks for data cache migration in chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
23. 
    Adaptive insertion policies for managing shared caches. [Citation Graph (, )][DBLP]
    
    
24. 
    Analysis and approximation of optimal co-scheduling on chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
25. 
    An adaptive resource partitioning algorithm for SMT processors. [Citation Graph (, )][DBLP]
    
    
26. 
    Meeting points: using thread criticality to adapt multicore hardware to parallel regions. [Citation Graph (, )][DBLP]
    
    
27. 
    Prediction models for multi-dimensional power-performance optimization on many cores. [Citation Graph (, )][DBLP]
    
    
28. 
    Mars: a MapReduce framework on graphics processors. [Citation Graph (, )][DBLP]
    
    
29. 
    Multi-mode energy management for multi-tier server clusters. [Citation Graph (, )][DBLP]
    
    
30. 
    A tuning framework for software-managed memory hierarchies. [Citation Graph (, )][DBLP]
    
    
31. 
    Hybrid access-specific software cache techniques for the cell BE architecture. [Citation Graph (, )][DBLP]
    
    
32. 
    COMIC: a coherent shared memory interface for cell be. [Citation Graph (, )][DBLP]