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Conferences in DBLP
(ddecs)
2009 (conf/ddecs/2009)
Design tools and circuit solutions for degradation-resilient analog circuits in nanometer CMOS. [Citation Graph (, )][DBLP]
Cognitive self-adaptive computing and communication systems: Test, control and adaptation. [Citation Graph (, )][DBLP]
Challenges for test and design for test. [Citation Graph (, )][DBLP]
An SOC platform for ADC test and measurement. [Citation Graph (, )][DBLP]
A scheme of logic self repair including local interconnects. [Citation Graph (, )][DBLP]
Investigating the linearity of MOSFET-only switched-capacitor DeltaSigma modulators under low-voltage condition. [Citation Graph (, )][DBLP]
Comparison of different test strategies on a mixed-signal circuit. [Citation Graph (, )][DBLP]
Case Study : A class E power amplifier for ISO-14443A. [Citation Graph (, )][DBLP]
Fast congestion-aware timing-driven placement for island FPGA. [Citation Graph (, )][DBLP]
Analysis and optimization of ring oscillator using sub-feedback scheme. [Citation Graph (, )][DBLP]
Improve clock gating through power-optimal enable function selection. [Citation Graph (, )][DBLP]
An utilisation of Boolean differential calculus in variables partition calculation for decomposition of logic functions. [Citation Graph (, )][DBLP]
A fast untestability proof for SAT-based ATPG. [Citation Graph (, )][DBLP]
The impact of EFSM composition on functional ATPG. [Citation Graph (, )][DBLP]
An efficient fault simulation technique for transition faults in non-scan sequential circuits. [Citation Graph (, )][DBLP]
Self-timed full adder designs based on hybrid input encoding. [Citation Graph (, )][DBLP]
Optimization concepts for self-healing asynchronous circuits. [Citation Graph (, )][DBLP]
Asynchronous two-level logic of reduced cost. [Citation Graph (, )][DBLP]
Low-voltage low-power double bulk mixer for direct conversion receiver in 65nm CMOS. [Citation Graph (, )][DBLP]
Low voltage LNA implementations in 90 nm CMOS technology for multistandard GNSS. [Citation Graph (, )][DBLP]
BIST assisted wideband digital compensation for MB-UWB transmitters. [Citation Graph (, )][DBLP]
Architecture model for approximate palindrome detection. [Citation Graph (, )][DBLP]
Packet header analysis and field extraction for multigigabit networks. [Citation Graph (, )][DBLP]
A symbolic RTL synthesis for LUT-based FPGAs. [Citation Graph (, )][DBLP]
Physical design oriented DRAM Neighborhood Pattern Sensitive Fault testing. [Citation Graph (, )][DBLP]
Using 3-valued memory representation for state space reduction in embedded assembly code model checking. [Citation Graph (, )][DBLP]
An on-line testing scheme for repairing purposes in Flash memories. [Citation Graph (, )][DBLP]
Power devices current monitoring using horizontal and vertical magnetic force sensor. [Citation Graph (, )][DBLP]
Measurement of power supply noise tolerance of self-timed processor. [Citation Graph (, )][DBLP]
Test scheme for switched-capacitor circuits by digital analyses. [Citation Graph (, )][DBLP]
Structural test of programmed FPGA circuits. [Citation Graph (, )][DBLP]
Low voltage precharge CMOS logic. [Citation Graph (, )][DBLP]
MDCT / IMDCT low power implementations in 90 nm CMOS technology for MP3 audio. [Citation Graph (, )][DBLP]
Effective mars rover platform design with Hardware / Software co-design. [Citation Graph (, )][DBLP]
On the role of the power supply as an entry for common cause faults - An experimental analysis. [Citation Graph (, )][DBLP]
An analysis of the timing behavior of CMOS digital blocks under Simultaneous Switching Noise conditions. [Citation Graph (, )][DBLP]
Effective BIST for crosstalk faults in interconnects. [Citation Graph (, )][DBLP]
MTPP - Modular Traffic Processing Platform. [Citation Graph (, )][DBLP]
Simulation and planning method for on-chip power distribution - An industry perspective. [Citation Graph (, )][DBLP]
Experience in Virtual Testing of RSD cyclic A/D converters. [Citation Graph (, )][DBLP]
A 1GHz-GBW operational amplifier for DVB-H receivers in 65nm CMOS. [Citation Graph (, )][DBLP]
0.5V 160-MHz 260uW all digital phase-locked loop. [Citation Graph (, )][DBLP]
0.18 µm CMOS UWB LNA with new feedback configuration for optimization low noise, high gain and small area. [Citation Graph (, )][DBLP]
Hardware solution of chaos based image encryption. [Citation Graph (, )][DBLP]
Diagnosis of faulty units in regular graphs under the PMC model. [Citation Graph (, )][DBLP]
All digital baseband 50 Mbps data recovery using 5× oversampling with 0.9 data unit interval clock jitter tolerance. [Citation Graph (, )][DBLP]
Contactless characterization of MEMS devices using optical microscopy. [Citation Graph (, )][DBLP]
A comprehensive approach for soft error tolerant Four State Logic. [Citation Graph (, )][DBLP]
High-level symbolic simulation for automatic model extraction. [Citation Graph (, )][DBLP]
Global parametric faults identification with the use of Differential Evolution. [Citation Graph (, )][DBLP]
Forward and backward guarding in early output logic. [Citation Graph (, )][DBLP]
Logic synthesis method for pattern matching circuits implementation in FPGA with embedded memories. [Citation Graph (, )][DBLP]
Contention-avoiding custom topology generation for network-on-chip. [Citation Graph (, )][DBLP]
Enhanced LEON3 core for superscalar processing. [Citation Graph (, )][DBLP]
Ultra low-voltage switched current mirror. [Citation Graph (, )][DBLP]
Self-timed thermal sensing and monitoring of multicore systems. [Citation Graph (, )][DBLP]
A CMOS bio-impedance measurement system. [Citation Graph (, )][DBLP]
An enhanced FPGA-based low-cost tester platform exploiting effective test data compression for SoCs. [Citation Graph (, )][DBLP]
Comprehensive bridging fault diagnosis based on the SLAT paradigm. [Citation Graph (, )][DBLP]
Round-level concurrent error detection applied to Advanced Encryption Standard. [Citation Graph (, )][DBLP]
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