Conferences in DBLP
A Dynamic Hybrid Cache Coherency Protocol for Shared-Memory MPSoC. [Citation Graph (, )][DBLP ] An Efficient Hardware Architecture for Packet Re-sequencing in Network Processors MPSoCs. [Citation Graph (, )][DBLP ] An Effective Replacement Strategy of Cache Memory for an SMT Processor. [Citation Graph (, )][DBLP ] An Evaluation of Behaviors of S-NUCA CMPs Running Scientific Workload. [Citation Graph (, )][DBLP ] A Priority-Based Budget Scheduler with Conservative Dataflow Model. [Citation Graph (, )][DBLP ] Improving the Performance of the Divide-Add Fused Operation Using Variable Latency Quotient Generation. [Citation Graph (, )][DBLP ] Distributed Collaborative Design of a Mixed-Signal IP Component. [Citation Graph (, )][DBLP ] A Hazard-Free Delay-Insensitive 4-phase On-Chip Link Using MVCM Signaling. [Citation Graph (, )][DBLP ] Improving Latency of Quantum Circuits by Gate Exchanging. [Citation Graph (, )][DBLP ] Run-Time Reconfigurable Array Using Magnetic RAM. [Citation Graph (, )][DBLP ] Robustness Check for Multiple Faults Using Formal Techniques. [Citation Graph (, )][DBLP ] Instruction Precomputation for Fault Detection. [Citation Graph (, )][DBLP ] Soft Error Tolerant Asynchronous Circuits Based on Dual Redundant Four State Logic. [Citation Graph (, )][DBLP ] High Availability Fault Tolerant Architectures Implemented into FPGAs. [Citation Graph (, )][DBLP ] Data Encoding for Low-Power in Wormhole-Switched Networks-on-Chip. [Citation Graph (, )][DBLP ] Exploration of Slot Allocation for On-Chip TDM Virtual Circuits. [Citation Graph (, )][DBLP ] Mapping Algorithms for NoC-Based Heterogeneous MPSoC Platforms. [Citation Graph (, )][DBLP ] Architectural Exploration of Per-Core DVFS for Energy-Constrained On-Chip Networks. [Citation Graph (, )][DBLP ] Power Management Aware Low Leakage Behavioural Synthesis. [Citation Graph (, )][DBLP ] Variation-tolerant Design Using Residue Number System. [Citation Graph (, )][DBLP ] Optimized Reconfigurable RTL Components for Performance Improvements During High-Level Synthesis. [Citation Graph (, )][DBLP ] Combined SD-RNS Constant Multiplication. [Citation Graph (, )][DBLP ] Temperature- and Cost-Aware Design of 3D Multiprocessor Architectures. [Citation Graph (, )][DBLP ] Calibration Method for a CMOS 0.06mm2 150MS/s 8-bit ADC. [Citation Graph (, )][DBLP ] Bootstrapped Adiabatic Complementary Pass-Transistor Logic Driver Circuit for Large Capacitive Load and Low-energy Applications. [Citation Graph (, )][DBLP ] An Adaptive Unicast/Multicast Routing Algorithm for MPSoCs. [Citation Graph (, )][DBLP ] Model-Driven Design of Embedded Multimedia Applications on SoCs. [Citation Graph (, )][DBLP ] GridRT: A Massively Parallel Architecture for Ray-Tracing Using Uniform Grids. [Citation Graph (, )][DBLP ] Using Integer Linear Programming in Test-bench Generation for Evaluating Communication Processors. [Citation Graph (, )][DBLP ] Reliability Estimation Process. [Citation Graph (, )][DBLP ] Time-Varying Network Fault Model for the Design of Dependable Networked Embedded Systems. [Citation Graph (, )][DBLP ] Block-Level Fault Model-Free Debug and Diagnosis in Digital Systems. [Citation Graph (, )][DBLP ] High Performance Image Processing on a Massively Parallel Processor Array. [Citation Graph (, )][DBLP ] Thermal-Aware Test Scheduling for Core-Based SoC in an Abort-on-First-Fail Test Environment. [Citation Graph (, )][DBLP ] Low Power Encoding in NoCs Based on Coupling Transition Avoidance. [Citation Graph (, )][DBLP ] Hierarchical NoCs for Optimized Access to Shared Memory and IO Resources. [Citation Graph (, )][DBLP ] Storage Architecture for an On-chip Multi-core Processor. [Citation Graph (, )][DBLP ] Double-precision Gauss-Jordan Algorithm with Partial Pivoting on FPGAs. [Citation Graph (, )][DBLP ] A Comparative Study of Parallel Prefix Adders in FPGA Implementation of EAC. [Citation Graph (, )][DBLP ] Streaming Reduction Circuit. [Citation Graph (, )][DBLP ] Variable Latency Rounding for Golschmidt Algorithm with Parallel Remainder Estimation. [Citation Graph (, )][DBLP ] Pulse Generation for On-chip Data Transmission. [Citation Graph (, )][DBLP ] High Performance Bootstrapped CMOS Dual Supply Level Shifter for 0.5V Input and 1V Output. [Citation Graph (, )][DBLP ] Performance-Effective Compaction of Standard-Cell Libraries for Digital Design. [Citation Graph (, )][DBLP ] On the Risk of Fault Coupling over the Chip Substrate. [Citation Graph (, )][DBLP ] Heterogeneous Multiprocessor Synthesis under Performance and Reliability Constraints. [Citation Graph (, )][DBLP ] A Hardware-Scheduler for Fault Detection in RTOS-Based Embedded Systems. [Citation Graph (, )][DBLP ] Reliable Railway Station System Based on Regular Structure Implemented in FPGA. [Citation Graph (, )][DBLP ] Dependable Controller Design Using Polymorphic Counters. [Citation Graph (, )][DBLP ] Internet-Router Buffered Crossbars Based on Networks on Chip. [Citation Graph (, )][DBLP ] Network-on-Chip Architecture Exploration Framework. [Citation Graph (, )][DBLP ] Meta-model Assisted Optimization for Design Space Exploration of Multi-Processor Systems-on-Chip. [Citation Graph (, )][DBLP ] Approximate-Timed Transactional Level Modeling for MPSoC Exploration: A Network-on-Chip Case Study. [Citation Graph (, )][DBLP ] A Standardized Knobs and Monitors RTL2RTL Insertion Methodology for Fine Grain SoC Tuning. [Citation Graph (, )][DBLP ] Conservative Dynamic Energy Management for Real-Time Dataflow Applications Mapped on Multiple Processors. [Citation Graph (, )][DBLP ] Compilation Technique for Loop Overhead Minimization. [Citation Graph (, )][DBLP ] Pipelining-Based High Throughput Low Energy Mapping on Network-on-Chip. [Citation Graph (, )][DBLP ] Open Platform for Prototyping of Advanced Software Defined Radio and Cognitive Radio Techniques. [Citation Graph (, )][DBLP ] Architecture and DSP Implementation of a DVB-S2 Baseband Demodulator. [Citation Graph (, )][DBLP ] An Open and Reconfigurable Platform for 4G Telecommunication: Concepts and Application. [Citation Graph (, )][DBLP ] Deductive Fault Simulation for Asynchronous Sequential Circuits. [Citation Graph (, )][DBLP ] ARROW - A Generic Hardware Fault Injection Tool for NoCs. [Citation Graph (, )][DBLP ] A Fault Tolerant NoC Architecture for Reliability Improvement and Latency Reduction. [Citation Graph (, )][DBLP ] Reliability Analysis of Qubit Data Movement for Distributed Quantum Computation. [Citation Graph (, )][DBLP ] High Reliable Remote Terminal Unit for Space Applications. [Citation Graph (, )][DBLP ] SIMD Architectural Enhancements to Improve the Performance of the 2D Discrete Wavelet Transform. [Citation Graph (, )][DBLP ] Simultaneous Multithreading VLIW DSP Architecture with Dynamic Dispatch Mechanism. [Citation Graph (, )][DBLP ] Iterative Algorithm for Compound Instruction Selection with Register Coalescing. [Citation Graph (, )][DBLP ] CPLD-oriented Synthesis of Finite State Machines. [Citation Graph (, )][DBLP ] Architecture-Driven Synthesis of Reconfigurable Cells. [Citation Graph (, )][DBLP ] An on Chip Network inside a FPGA for Run-Time Reconfigurable Low Latency Grid Communication. [Citation Graph (, )][DBLP ] Composable Resource Sharing Based on Latency-Rate Servers. [Citation Graph (, )][DBLP ] A MPSoC Prototyping Platform for Flexible Radio Applications. [Citation Graph (, )][DBLP ] Abstract Description of System Application and Hardware Architecture for Hardware/Software Code Generation. [Citation Graph (, )][DBLP ] Reconfiguration Level Analysis of FFT / FIR Units in Wireless Telecommunication Systems. [Citation Graph (, )][DBLP ] Flexible Architectures for LDPC Decoders Based on Network on Chip Paradigm. [Citation Graph (, )][DBLP ] High Performance CMOS 2-input NAND Based on Low-race Split-level Charge-recycling Pass-transistor Logic. [Citation Graph (, )][DBLP ] Power Aware Fulfilment of Latency Requirements by Exploiting Heterogeneity in Wireless Sensor and Actuator Networks. [Citation Graph (, )][DBLP ] The Case for a Balanced Decomposition Process. [Citation Graph (, )][DBLP ] Heuristic Synthesis of Multi-Terminal BDDs Based on Local Width/Cost Minimization. [Citation Graph (, )][DBLP ] Design, Simulation and Performance Evaluation of a NAND Based Single-electron 2-4 Decoder. [Citation Graph (, )][DBLP ] Adaptive Dynamic Voltage and Frequency Scaling Algorithm for Symmetric Multiprocessor Architecture. [Citation Graph (, )][DBLP ] Survey of Test Data Compression Technique Emphasizing Code Based Schemes. [Citation Graph (, )][DBLP ] A Concept for Logic Self Repair. [Citation Graph (, )][DBLP ] A Synthesisable Quasi-Delay Insensitive Result Forwarding Unit for an Asynchronous Processor. [Citation Graph (, )][DBLP ] An Efficient Low-Complexity Alternative to the ROB for Out-of-Order Retirement of Instructions. [Citation Graph (, )][DBLP ] An Effective Methodology to Multi-objective Design of Application Domain-specific Embedded Architectures. [Citation Graph (, )][DBLP ] Energy and Performance Model of a SPARC Leon3 Processor. [Citation Graph (, )][DBLP ] Acceleration of MELP Algorithm Using DSP Coprocessor with Extended Registers. [Citation Graph (, )][DBLP ] FPGA Accelerator for RNA Secondary Structure Prediction. [Citation Graph (, )][DBLP ] An FPGA-Based Embedded System for Fingerprint Matching Using Phase-Only Correlation Algorithm. [Citation Graph (, )][DBLP ] xMAML: A Modeling Language for Dynamically Reconfigurable Architectures. [Citation Graph (, )][DBLP ] A High Performance Hardware Architecture for One Bit Transform Based Motion Estimation. [Citation Graph (, )][DBLP ] Memory Conflict Analysis and Interleaver Design for Parallel Turbo Decoding Supporting HSPA Evolution. [Citation Graph (, )][DBLP ] GPU Accelerated Solver of Time-Dependent Air Pollutant Transport Equations. [Citation Graph (, )][DBLP ] A Reconfigurable Frame Interpolation Hardware Architecture for High Definition Video. [Citation Graph (, )][DBLP ] Transactions Sequence Tracking by means of Dynamic Binary Instrumentation of TLM Models. [Citation Graph (, )][DBLP ] Design of a Highly Dependable Beamforming Chip. [Citation Graph (, )][DBLP ] One Dimensional Systolic Inversion Architecture Based on Modified GF(2^k) Extended Euclidean Algorithm. [Citation Graph (, )][DBLP ] Signal Integrity and Power Integrity Methodology for Robust Analysis of On-the-Board System for High Speed Serial Links. [Citation Graph (, )][DBLP ] Synthesizing Reversible Circuits for Irreversible Functions. [Citation Graph (, )][DBLP ] A Fast SOP Minimizer for Logic Funcions Described by Many Product Terms. [Citation Graph (, )][DBLP ] Representation of Incompletely Specified Index Generation Functions Using Minimal Number of Compound Variables. [Citation Graph (, )][DBLP ] Logic Minimization and Testability of 2SPP-P-Circuits. [Citation Graph (, )][DBLP ] FPGA Implementations of SHA-3 Candidates: CubeHash, Grostl, LANE, Shabal and Spectral Hash. [Citation Graph (, )][DBLP ] Recursive Systematic Convolutional Code Simulation for Ofdm - 802.11p System and FPGA Implementation Using an ESL Methodology. [Citation Graph (, )][DBLP ] Stereo Vision Algorithm Implementation in FPGA Using Census Transform for Effective Resource Optimization. [Citation Graph (, )][DBLP ] The Parallel Sieve Method for a Virus Scanning Engine. [Citation Graph (, )][DBLP ] Low-Power Low-Energy Prime-Field ECC Processor Based on Montgomery Modular Inverse Algorithm. [Citation Graph (, )][DBLP ] Methodology for Fast Pattern Matching by Deterministic Finite Automaton with Perfect Hashing. [Citation Graph (, )][DBLP ] An FPGA-Based Embedded System for a Sailing Robot. [Citation Graph (, )][DBLP ] Ad-hoc WSN in Biological Research. [Citation Graph (, )][DBLP ] Low Power Free Space Optical Communication in Wireless Sensor Networks. [Citation Graph (, )][DBLP ] A Framework for Compile-time and Run-time Management of Non-functional Aspects in WSNs Nodes. [Citation Graph (, )][DBLP ] Remote Monitoring of Thermal Performance of Salinity Gradient Solar Ponds. [Citation Graph (, )][DBLP ] 