Conferences in DBLP

Field-Programmable Custom Computing Machines (FCCM) (fccm)
2009 (conf/fccm/2009)

1. 
   On-Orbit Flight Results from the Reconfigurable Cibola Flight Experiment Satellite (CFESat). [Citation Graph (, )][DBLP]
   
   
2. 
   Accelerating Cosmological Data Analysis with FPGAs. [Citation Graph (, )][DBLP]
   
   
3. 
   FPGA Design Analysis of the Clustering Algorithm for the CERN Large Hadron Collider. [Citation Graph (, )][DBLP]
   
   
4. 
   Accelerating Quadrature Methods for Option Valuation. [Citation Graph (, )][DBLP]
   
   
5. 
   Accelerating SPICE Model-Evaluation using FPGAs. [Citation Graph (, )][DBLP]
   
   
6. 
   FPGA Accelerated Simulation of Biologically Plausible Spiking Neural Networks. [Citation Graph (, )][DBLP]
   
   
7. 
   Generic Software Framework for Adaptive Applications on FPGAs. [Citation Graph (, )][DBLP]
   
   
8. 
   Block, Drop or Roll(back): Alternative Preemption Methods for RH Multi-Tasking. [Citation Graph (, )][DBLP]
   
   
9. 
   Size-Reconfiguration Delay Tradeoffs for a Class of DSP Blocks in Multi-mode Communication Systems. [Citation Graph (, )][DBLP]
   
   
10. 
    CAAD BLASTP: NCBI BLASTP Accelerated with FPGA-Based Accelerated Pre-Filtering. [Citation Graph (, )][DBLP]
    
    
11. 
    RC-BLASTn: Implementation and Evaluation of the BLASTn Scan Function. [Citation Graph (, )][DBLP]
    
    
12. 
    Multi-Core Architecture on FPGA for Large Dictionary String Matching. [Citation Graph (, )][DBLP]
    
    
13. 
    Memory-Efficient Pipelined Architecture for Large-Scale String Matching. [Citation Graph (, )][DBLP]
    
    
14. 
    A Massively Parallel FPGA-Based Coprocessor for Support Vector Machines. [Citation Graph (, )][DBLP]
    
    
15. 
    Application Specific Customization and Scalability of Soft Multiprocessors. [Citation Graph (, )][DBLP]
    
    
16. 
    Benchmarking Reconfigurable Architectures in the Mobile Domain. [Citation Graph (, )][DBLP]
    
    
17. 
    Optical Flow on the Ambric Massively Parallel Processor Array (MPPA). [Citation Graph (, )][DBLP]
    
    
18. 
    Real-Time Fisheye Lens Distortion Correction Using Automatically Generated Streaming Accelerators. [Citation Graph (, )][DBLP]
    
    
19. 
    FPGA-based Monte Carlo Computation of Light Absorption for Photodynamic Cancer Therapy. [Citation Graph (, )][DBLP]
    
    
20. 
    Scalable High Throughput and Power Efficient IP-Lookup on FPGA. [Citation Graph (, )][DBLP]
    
    
21. 
    Architectural Comparison of Instruments for Transaction Level Monitoring of FPGA-Based Packet Processing Systems. [Citation Graph (, )][DBLP]
    
    
22. 
    A Fine-grained Pipelined Implementation of the LINPACK Benchmark on FPGAs. [Citation Graph (, )][DBLP]
    
    
23. 
    Compact and Flexible Microcoded Elliptic Curve Processor for Reconfigurable Devices. [Citation Graph (, )][DBLP]
    
    
24. 
    Non-Preconditioned Conjugate Gradient on Cell and FPGA Based Hybrid Supercomputer Nodes. [Citation Graph (, )][DBLP]
    
    
25. 
    More Flops or More Precision? Accuracy Parameterizable Linear Equation Solvers for Model Predictive Control. [Citation Graph (, )][DBLP]
    
    
26. 
    In-situ FPGA Debug Driven by On-Board Microcontroller. [Citation Graph (, )][DBLP]
    
    
27. 
    Exploiting Matrix Symmetry to Improve FPGA-Accelerated Conjugate Gradient. [Citation Graph (, )][DBLP]
    
    
28. 
    Accelerating the Gauss-Seidel Power Flow Solver on a High Performance Reconfigurable Computer. [Citation Graph (, )][DBLP]
    
    
29. 
    Evaluation of Static Analysis Techniques for Fixed-Point Precision Optimization. [Citation Graph (, )][DBLP]
    
    
30. 
    A Packet Generator on the NetFPGA Platform. [Citation Graph (, )][DBLP]
    
    
31. 
    Shared Memory Cache Organizations for Reconfigurable Computing Systems. [Citation Graph (, )][DBLP]
    
    
32. 
    Exploiting Partially Reconfigurable FPGAs for Situation-Based Reconfiguration in Wireless Sensor Networks. [Citation Graph (, )][DBLP]
    
    
33. 
    Efficient Mapping of Hardware Tasks on Reconfigurable Computers Using Libraries of Architecture Variants. [Citation Graph (, )][DBLP]
    
    
34. 
    Minimizing Internal Fragmentation by Fine-Grained Two-Dimensional Module Placement for Runtime Reconfiguralble Systems. [Citation Graph (, )][DBLP]
    
    
35. 
    Acceleration and Energy Efficiency of a Geometric Algebra Computation using Reconfigurable Computers and GPUs. [Citation Graph (, )][DBLP]
    
    
36. 
    FPGA Floating Point Datapath Compiler. [Citation Graph (, )][DBLP]
    
    
37. 
    A Parameterized Stereo Vision Core for FPGAs. [Citation Graph (, )][DBLP]
    
    
38. 
    FPGA Implementation of a Single-Precision Floating-Point Multiply-Accumulator with Single-Cycle Accumulation. [Citation Graph (, )][DBLP]
    
    
39. 
    AIREN: A Novel Integration of On-Chip and Off-Chip FPGA Networks. [Citation Graph (, )][DBLP]
    
    
40. 
    IMORC: Application Mapping, Monitoring and Optimization for High-Performance Reconfigurable Computing. [Citation Graph (, )][DBLP]
    
    
41. 
    Optimal Placement-aware Trace-Based Scheduling of Hardware Reconfigurations for FPGA Accelerators. [Citation Graph (, )][DBLP]
    
    
42. 
    Employment of Reduced Precision Redundancy for Fault Tolerant FPGA Applications. [Citation Graph (, )][DBLP]
    
    
43. 
    High. [Citation Graph (, )][DBLP]
    
    
44. 
    Application Experiments: MPPA and FPGA. [Citation Graph (, )][DBLP]
    
    
45. 
    FPGA Implementation of the Interior-Point Algorithm with Applications to Collision Detection. [Citation Graph (, )][DBLP]
    
    
46. 
    Design Exploration for FPGA-Based Multiprocessor Architecture: JPEG Encoding Case Study. [Citation Graph (, )][DBLP]
    
    
47. 
    An FPGA Implementation for Solving Least Square Problem. [Citation Graph (, )][DBLP]