Conferences in DBLP

International Symposium om Computer Architecture (ISCA) (isca)
2009 (conf/isca/2009)

1. 
   Ten ways to waste a parallel computer. [Citation Graph (, )][DBLP]
   
   
2. 
   Architecting phase change memory as a scalable dram alternative. [Citation Graph (, )][DBLP]
   
   
3. 
   A durable and energy efficient main memory using phase change memory technology. [Citation Graph (, )][DBLP]
   
   
4. 
   Scalable high performance main memory system using phase-change memory technology. [Citation Graph (, )][DBLP]
   
   
5. 
   Hybrid cache architecture with disparate memory technologies. [Citation Graph (, )][DBLP]
   
   
6. 
   Dynamic MIPS rate stabilization in out-of-order processors. [Citation Graph (, )][DBLP]
   
   
7. 
   Hardware support for WCET analysis of hard real-time multicore systems. [Citation Graph (, )][DBLP]
   
   
8. 
   Spatio-temporal memory streaming. [Citation Graph (, )][DBLP]
   
   
9. 
   Stream chaining: exploiting multiple levels of correlation in data prefetching. [Citation Graph (, )][DBLP]
   
   
10. 
    Architectural core salvaging in a multi-core processor for hard-error tolerance. [Citation Graph (, )][DBLP]
    
    
11. 
    End-to-end register data-flow continuous self-test. [Citation Graph (, )][DBLP]
    
    
12. 
    Memory mapped ECC: low-cost error protection for last level caches. [Citation Graph (, )][DBLP]
    
    
13. 
    AnySP: anytime anywhere anyway signal processing. [Citation Graph (, )][DBLP]
    
    
14. 
    Rigel: an architecture and scalable programming interface for a 1000-core accelerator. [Citation Graph (, )][DBLP]
    
    
15. 
    An analytical model for a GPU architecture with memory-level and thread-level parallelism awareness. [Citation Graph (, )][DBLP]
    
    
16. 
    Multi-execution: multicore caching for data-similar executions. [Citation Graph (, )][DBLP]
    
    
17. 
    PIPP: promotion/insertion pseudo-partitioning of multi-core shared caches. [Citation Graph (, )][DBLP]
    
    
18. 
    Reactive NUCA: near-optimal block placement and replication in distributed caches. [Citation Graph (, )][DBLP]
    
    
19. 
    A case for bufferless routing in on-chip networks. [Citation Graph (, )][DBLP]
    
    
20. 
    Application-aware deadlock-free oblivious routing. [Citation Graph (, )][DBLP]
    
    
21. 
    Indirect adaptive routing on large scale interconnection networks. [Citation Graph (, )][DBLP]
    
    
22. 
    Internet-scale service infrastructure efficiency. [Citation Graph (, )][DBLP]
    
    
23. 
    InvisiFence: performance-transparent memory ordering in conventional multiprocessors. [Citation Graph (, )][DBLP]
    
    
24. 
    Decoupled store completion/silent deterministic replay: enabling scalable data memory for CPR/CFP processors. [Citation Graph (, )][DBLP]
    
    
25. 
    Decoupled DIMM: building high-bandwidth memory system using low-speed DRAM devices. [Citation Graph (, )][DBLP]
    
    
26. 
    Disaggregated memory for expansion and sharing in blade servers. [Citation Graph (, )][DBLP]
    
    
27. 
    The performance of PC solid-state disks (SSDs) as a function of bandwidth, concurrency, device architecture, and system organization. [Citation Graph (, )][DBLP]
    
    
28. 
    Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
29. 
    Thread motion: fine-grained power management for multi-core systems. [Citation Graph (, )][DBLP]
    
    
30. 
    Temperature-constrained power control for chip multiprocessors with online model estimation. [Citation Graph (, )][DBLP]
    
    
31. 
    A case for an interleaving constrained shared-memory multi-processor. [Citation Graph (, )][DBLP]
    
    
32. 
    SigRace: signature-based data race detection. [Citation Graph (, )][DBLP]
    
    
33. 
    ECMon: exposing cache events for monitoring. [Citation Graph (, )][DBLP]
    
    
34. 
    End-to-end performance forecasting: finding bottlenecks before they happen. [Citation Graph (, )][DBLP]
    
    
35. 
    Scaling the bandwidth wall: challenges in and avenues for CMP scaling. [Citation Graph (, )][DBLP]
    
    
36. 
    A fault tolerant, area efficient architecture for Shor's factoring algorithm. [Citation Graph (, )][DBLP]
    
    
37. 
    Performance and power of cache-based reconfigurable computing. [Citation Graph (, )][DBLP]
    
    
38. 
    A memory system design framework: creating smart memories. [Citation Graph (, )][DBLP]
    
    
39. 
    Flexible reference-counting-based hardware acceleration for garbage collection. [Citation Graph (, )][DBLP]
    
    
40. 
    Firefly: illuminating future network-on-chip with nanophotonics. [Citation Graph (, )][DBLP]
    
    
41. 
    Phastlane: a rapid transit optical routing network. [Citation Graph (, )][DBLP]
    
    
42. 
    Achieving predictable performance through better memory controller placement in many-core CMPs. [Citation Graph (, )][DBLP]
    
    
43. 
    Dynamic performance tuning for speculative threads. [Citation Graph (, )][DBLP]
    
    
44. 
    Boosting single-thread performance in multi-core systems through fine-grain multi-threading. [Citation Graph (, )][DBLP]
    
    
45. 
    Simultaneous speculative threading: a novel pipeline architecture implemented in sun's rock processor. [Citation Graph (, )][DBLP]