Conferences in DBLP

International Symposium on Low Power Electronics and Design (islped)
2009 (conf/islped/2009)

1. 
   Advances in process technology & IBM collaborative ecosystem for leadership power performance SOC designs. [Citation Graph (, )][DBLP]
   
   
2. 
   Nanometer MOSFET effects on the minimum-energy point of 45nm subthreshold logic. [Citation Graph (, )][DBLP]
   
   
3. 
   Design and analysis of ultra-thin-body SOI based subthreshold SRAM. [Citation Graph (, )][DBLP]
   
   
4. 
   Slew-aware clock tree design for reliable subthreshold circuits. [Citation Graph (, )][DBLP]
   
   
5. 
   Technology flavor selection and adaptive techniques for timing-constrained 45nm subthreshold circuits. [Citation Graph (, )][DBLP]
   
   
6. 
   Serial sub-threshold circuits for ultra-low-power systems. [Citation Graph (, )][DBLP]
   
   
7. 
   Hybrid logical-statistical simulation with thermal and IR-drop mapping for degradation and variation prediction. [Citation Graph (, )][DBLP]
   
   
8. 
   Variation-aware supply voltage assignment for minimizing circuit degradation and leakage. [Citation Graph (, )][DBLP]
   
   
9. 
   A centralized supply voltage and local body bias-based compensation approach to mitigate within-die process variation. [Citation Graph (, )][DBLP]
   
   
10. 
    Tuning-friendly body bias clustering for compensating random variability in subthreshold circuits. [Citation Graph (, )][DBLP]
    
    
11. 
    Statistical static timing analysis considering leakage variability in power gated designs. [Citation Graph (, )][DBLP]
    
    
12. 
    A low power high noise immunity boost DC-DC converter using the differential difference amplifiers. [Citation Graph (, )][DBLP]
    
    
13. 
    A single inductor dual input dual output DC-DC converter with hybrid supplies for solar energy harvesting applications. [Citation Graph (, )][DBLP]
    
    
14. 
    A CMOS low power current-mode polyphase filter. [Citation Graph (, )][DBLP]
    
    
15. 
    Improvement of power efficiency in switched capacitor DC-DC converter by shoot-through current elimination. [Citation Graph (, )][DBLP]
    
    
16. 
    Inductor design of 20-V boost converter for low power 3D solid state drive with NAND flash memories. [Citation Graph (, )][DBLP]
    
    
17. 
    PPT: joint performance/power/thermal management of DRAM memory for multi-core systems. [Citation Graph (, )][DBLP]
    
    
18. 
    Predict and act: dynamic thermal management for multi-core processors. [Citation Graph (, )][DBLP]
    
    
19. 
    Online work maximization under a peak temperature constraint. [Citation Graph (, )][DBLP]
    
    
20. 
    Dynamic thermal management using thin-film thermoelectric cooling. [Citation Graph (, )][DBLP]
    
    
21. 
    A 2.6 µW sub-threshold mixed-signal ECG SoC. [Citation Graph (, )][DBLP]
    
    
22. 
    A 0.9V, 65nm logic-compatible embedded DRAM with > 1ms data retention time and 53% less static power than a power-gated SRAM. [Citation Graph (, )][DBLP]
    
    
23. 
    Frequency and yield optimization using power gates in power-constrained designs. [Citation Graph (, )][DBLP]
    
    
24. 
    NBTI-aware power gating for concurrent leakage and aging optimization. [Citation Graph (, )][DBLP]
    
    
25. 
    The opportunity cost of low power design: a case study in circuit tuning. [Citation Graph (, )][DBLP]
    
    
26. 
    Behavior-level observability don't-cares and application to low-power behavioral synthesis. [Citation Graph (, )][DBLP]
    
    
27. 
    Minimizing data center cooling and server power costs. [Citation Graph (, )][DBLP]
    
    
28. 
    Thinking outside the box: power management at the system level & beyond. [Citation Graph (, )][DBLP]
    
    
29. 
    A look inside IBM's green data center research. [Citation Graph (, )][DBLP]
    
    
30. 
    Sustainable IT ecosystems and data centers. [Citation Graph (, )][DBLP]
    
    
31. 
    Circuit design in nano-scale CMOS era: opportunities & challenges. [Citation Graph (, )][DBLP]
    
    
32. 
    Way-tagged cache: an energy-efficient L2 cache architecture under write-through policy. [Citation Graph (, )][DBLP]
    
    
33. 
    Way guard: a segmented counting bloom filter approach to reducing energy for set-associative caches. [Citation Graph (, )][DBLP]
    
    
34. 
    Energy-efficient renaming with register versioning. [Citation Graph (, )][DBLP]
    
    
35. 
    Cooperative shared resource access control for low-power chip multiprocessors. [Citation Graph (, )][DBLP]
    
    
36. 
    An energy-efficient checkpointing mechanism for out of order commit processor. [Citation Graph (, )][DBLP]
    
    
37. 
    Analyzing potential power reduction with adaptive voltage positioning optimized for multicore processors. [Citation Graph (, )][DBLP]
    
    
38. 
    Significance driven computation: a voltage-scalable, variation-aware, quality-tuning motion estimator. [Citation Graph (, )][DBLP]
    
    
39. 
    Optimizing total power of many-core processors considering voltage scaling limit and process variations. [Citation Graph (, )][DBLP]
    
    
40. 
    Integrating dynamic voltage/frequency scaling and adaptive body biasing using test-time voltage selection. [Citation Graph (, )][DBLP]
    
    
41. 
    Pulse width modulation for reduced peak power full-swing on-chip interconnect. [Citation Graph (, )][DBLP]
    
    
42. 
    Low power circuit design based on heterojunction tunneling transistors (HETTs). [Citation Graph (, )][DBLP]
    
    
43. 
    A 45nm CMOS 0.35v-optimized standard cell library for ultra-low power applications. [Citation Graph (, )][DBLP]
    
    
44. 
    A low power 3D integrated FFT engine using hypercube memory division. [Citation Graph (, )][DBLP]
    
    
45. 
    Data manipulation techniques to reduce phase change memory write energy. [Citation Graph (, )][DBLP]
    
    
46. 
    vGreen: a system for energy efficient computing in virtualized environments. [Citation Graph (, )][DBLP]
    
    
47. 
    Near optimal battery-aware energy management. [Citation Graph (, )][DBLP]
    
    
48. 
    Transaction-based adaptive dynamic voltage scaling for interactive applications. [Citation Graph (, )][DBLP]
    
    
49. 
    Tracking the power in an enterprise decision support system. [Citation Graph (, )][DBLP]
    
    
50. 
    Ranking servers based on energy savings for computation offloading. [Citation Graph (, )][DBLP]
    
    
51. 
    Leakage- and variability-conscious circuit designs for the 0.5-v nanoscale CMOS era. [Citation Graph (, )][DBLP]
    
    
52. 
    Non volatile memories to enable system power scaling. [Citation Graph (, )][DBLP]
    
    
53. 
    Low voltage tunnel transistor architecture and its viability for energy efficient logic applications. [Citation Graph (, )][DBLP]
    
    
54. 
    Cross-over current suppressing latch compared to state-of-the-art for low-power low-frequency applications with resonant clocking. [Citation Graph (, )][DBLP]
    
    
55. 
    Reducing the leakage and timing variability of 2D ICcs using 3D ICs. [Citation Graph (, )][DBLP]
    
    
56. 
    An optimization strategy for low energy and high performance for the on-chip interconnect signalling. [Citation Graph (, )][DBLP]
    
    
57. 
    A high-performance low-power nanophotonic on-chip network. [Citation Graph (, )][DBLP]
    
    
58. 
    Exploration of 3D stacked L2 cache design for high performance and efficient thermal control. [Citation Graph (, )][DBLP]
    
    
59. 
    Power-management-based Chien search for low power BCH decoder. [Citation Graph (, )][DBLP]
    
    
60. 
    Low power robust signal processing. [Citation Graph (, )][DBLP]
    
    
61. 
    Enabling ultra low voltage system operation by tolerating on-chip cache failures. [Citation Graph (, )][DBLP]
    
    
62. 
    Design of multi-mode 4-switch buck-boost controller. [Citation Graph (, )][DBLP]
    
    
63. 
    Electromigration study of power-gated grids. [Citation Graph (, )][DBLP]
    
    
64. 
    A novel 0.5 V 15 µW 1.3 MHz temperature-compensated analog PWM-controller for switch-mode converters. [Citation Graph (, )][DBLP]
    
    
65. 
    SOI, interconnect, package, and mainboard thermal characterization. [Citation Graph (, )][DBLP]
    
    
66. 
    N-version temperature-aware scheduling and binding. [Citation Graph (, )][DBLP]
    
    
67. 
    Energy-aware instruction-set customization for real-time embedded multiprocessor systems. [Citation Graph (, )][DBLP]
    
    
68. 
    Power-saving color transformation of mobile graphical user interfaces on OLED-based displays. [Citation Graph (, )][DBLP]
    
    
69. 
    An energy-delay efficient 2-level data cache architecture for embedded system. [Citation Graph (, )][DBLP]
    
    
70. 
    Experimental analysis of sequence dependence on energy saving for error tolerant image processing. [Citation Graph (, )][DBLP]
    
    
71. 
    A programmable implementation of neural signal processing on a smartdust for brain-computer interfaces. [Citation Graph (, )][DBLP]
    
    
72. 
    An experimental validation of system level design space exploration methodology for energy efficient sensor nodes. [Citation Graph (, )][DBLP]
    
    
73. 
    It is all about power analysis, exploration and trade-offs. [Citation Graph (, )][DBLP]
    
    
74. 
    Challenges and opportunities in low-power design enablement. [Citation Graph (, )][DBLP]
    
    
75. 
    Dealing with disaggregation in ever-changing world of semiconductors. [Citation Graph (, )][DBLP]
    
    
76. 
    A 60fps 496mW multi-object recognition processor with workload-aware dynamic power management. [Citation Graph (, )][DBLP]
    
    
77. 
    The design of a bloom filter hardware accelerator for ultra low power systems. [Citation Graph (, )][DBLP]
    
    
78. 
    Dynamic power gating with quality guarantees. [Citation Graph (, )][DBLP]
    
    
79. 
    End-to-end validation of architectural power models. [Citation Graph (, )][DBLP]
    
    
80. 
    Low power fast and dense longest prefix match content addressable memory for IP routers. [Citation Graph (, )][DBLP]
    
    
81. 
    MicroFix: exploiting path-grained timing adaptability for improving power-performance efficiency. [Citation Graph (, )][DBLP]
    
    
82. 
    Adaptive RF chain management for energy-efficient spatial-multiplexing MIMO transmission. [Citation Graph (, )][DBLP]
    
    
83. 
    Remote progressive firmware update for flash-based networked embedded systems. [Citation Graph (, )][DBLP]
    
    
84. 
    Power management in energy harvesting embedded systems with discrete service levels. [Citation Graph (, )][DBLP]
    
    
85. 
    Energy efficient sampling for event detection in wireless sensor networks. [Citation Graph (, )][DBLP]
    
    
86. 
    Ultra low voltage CMOS. [Citation Graph (, )][DBLP]
    
    
87. 
    Emerging technologies and their impact on system design. [Citation Graph (, )][DBLP]
    
    
88. 
    Green transistors to green architectures. [Citation Graph (, )][DBLP]
    
    
89. 
    Green at the micro-scale: towards self-powered embedded systems. [Citation Graph (, )][DBLP]