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Conferences in DBLP
(ispass)
2006 (conf/ispass/2006)
RAMP: research accelerator for multiple processors - a community vision for a shared experimental parallel HW/SW platform. [Citation Graph (, )][DBLP]
Simulation sampling with live-points. [Citation Graph (, )][DBLP]
Accelerating architectural exploration using canonical instruction segments. [Citation Graph (, )][DBLP]
Branch trace compression for snapshot-based simulation. [Citation Graph (, )][DBLP]
Critical path analysis of the TRIPS architecture. [Citation Graph (, )][DBLP]
Characterizing the branch misprediction penalty. [Citation Graph (, )][DBLP]
Revisiting the performance impact of branch predictor latencies. [Citation Graph (, )][DBLP]
Evaluating the efficacy of statistical simulation for design space exploration. [Citation Graph (, )][DBLP]
Comparing simulation techniques for microarchitecture-aware floorplanning. [Citation Graph (, )][DBLP]
A statistical multiprocessor cache model. [Citation Graph (, )][DBLP]
Power efficient resource scaling in partitioned architectures through dynamic heterogeneity. [Citation Graph (, )][DBLP]
Compiler-based adaptive fetch throttling for energy-efficiency. [Citation Graph (, )][DBLP]
Modeling TCAM power for next generation network devices. [Citation Graph (, )][DBLP]
Quantitative system design. [Citation Graph (, )][DBLP]
Comparing multinomial and k-means clustering for SimPoint. [Citation Graph (, )][DBLP]
Considering all starting points for simultaneous multithreading simulation. [Citation Graph (, )][DBLP]
Automatic testcase synthesis and performance model validation for high performance PowerPC processors. [Citation Graph (, )][DBLP]
Improved stride prefetching using extrinsic stream characteristics. [Citation Graph (, )][DBLP]
Friendly fire: understanding the effects of multiprocessor prefetches. [Citation Graph (, )][DBLP]
MESA: reducing cache conflicts by integrating static and run-time methods. [Citation Graph (, )][DBLP]
Performance modeling and prediction for scientific Java applications. [Citation Graph (, )][DBLP]
Assessing the impact of reactive workloads on the performance of Web applications. [Citation Graph (, )][DBLP]
Workload sanitation for performance evaluation. [Citation Graph (, )][DBLP]
ATTILA: a cycle-level execution-driven simulator for modern GPU architectures. [Citation Graph (, )][DBLP]
Acquisition and evaluation of long DDR2-SDRAM access sequences. [Citation Graph (, )][DBLP]
Aestimo: a feedback-directed optimization evaluation tool. [Citation Graph (, )][DBLP]
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