Conferences in DBLP

(ispass)
2007 (conf/ispass/2007)

1. 
   Workloads, Scalability, and QoS Considerations in CMP Platforms. [Citation Graph (, )][DBLP]
   
   
2. 
   Performance Modeling and Analysis for AMD's High Performance Microprocessors. [Citation Graph (, )][DBLP]
   
   
3. 
   Accelerating Full-System Simulation through Characterizing and Predicting Operating System Performance. [Citation Graph (, )][DBLP]
   
   
4. 
   A Comparison of Two Approaches to Parallel Simulation of Multiprocessors. [Citation Graph (, )][DBLP]
   
   
5. 
   PTLsim: A Cycle Accurate Full System x86-64 Microarchitectural Simulator. [Citation Graph (, )][DBLP]
   
   
6. 
   Understanding the Memory Performance of Data-Mining Workloads on Small, Medium, and Large-Scale CMPs Using Hardware-Software Co-simulation. [Citation Graph (, )][DBLP]
   
   
7. 
   Characterizing a Complex J2EE Workload: A Comprehensive Analysis and Opportunities for Optimizations. [Citation Graph (, )][DBLP]
   
   
8. 
   Performance Characterization of Decimal Arithmetic in Commercial Java Workloads. [Citation Graph (, )][DBLP]
   
   
9. 
   Performance Impact of Unaligned Memory Operations in SIMD Extensions for Video Codec Applications. [Citation Graph (, )][DBLP]
   
   
10. 
    Combining Simulation and Virtualization through Dynamic Sampling. [Citation Graph (, )][DBLP]
    
    
11. 
    Phase-Guided Small-Sample Simulation. [Citation Graph (, )][DBLP]
    
    
12. 
    DRAM-Level Prefetching for Fully-Buffered DIMM: Design, Performance and Power Saving. [Citation Graph (, )][DBLP]
    
    
13. 
    Last-Touch Correlated Data Streaming. [Citation Graph (, )][DBLP]
    
    
14. 
    Using Model Trees for Computer Architecture Performance Analysis of Software Applications. [Citation Graph (, )][DBLP]
    
    
15. 
    Modeling and Single-Pass Simulation of CMP Cache Capacity and Accessibility. [Citation Graph (, )][DBLP]
    
    
16. 
    Using Wavelet Domain Workload Execution Characteristics to Improve Accuracy, Scalability and Robustness in Program Phase Analysis. [Citation Graph (, )][DBLP]
    
    
17. 
    Modeling and Characterizing Power Variability in Multicore Architectures. [Citation Graph (, )][DBLP]
    
    
18. 
    Complete System Power Estimation: A Trickle-Down Approach Based on Performance Events. [Citation Graph (, )][DBLP]
    
    
19. 
    An Analysis of Microarchitecture Vulnerability to Soft Errors on Simultaneous Multithreaded Architectures. [Citation Graph (, )][DBLP]
    
    
20. 
    Cross Binary Simulation Points. [Citation Graph (, )][DBLP]
    
    
21. 
    Reverse State Reconstruction for Sampled Microarchitectural Simulation. [Citation Graph (, )][DBLP]
    
    
22. 
    An Analysis of Performance Interference Effects in Virtual Environments. [Citation Graph (, )][DBLP]
    
    
23. 
    Performance Analysis of Cell Broadband Engine for High Memory Bandwidth Applications. [Citation Graph (, )][DBLP]
    
    
24. 
    Benefits of I/O Acceleration Technology (I/OAT) in Clusters. [Citation Graph (, )][DBLP]
    
    
25. 
    CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications. [Citation Graph (, )][DBLP]
    
    
26. 
    Simplifying Active Memory Clusters by Leveraging Directory Protocol Threads. [Citation Graph (, )][DBLP]