Small embeddable NBTI sensors (SENS) for tracking on-chip performance decay. [Citation Graph (, )][DBLP]
A unified FinFET reliability model including high K gate stack dynamic threshold voltage, hot carrier injection, and negative bias temperature instability. [Citation Graph (, )][DBLP]
On the efficacy of input Vector Control to mitigate NBTI effects and leakage power. [Citation Graph (, )][DBLP]
Power & variability test chip architecture and 45nm-generation silicon-based analysis for robust, power-aware SoC design. [Citation Graph (, )][DBLP]
On-chip dynamic worst-case crosstalk pattern detection and elimination for bus-based macro-cell designs. [Citation Graph (, )][DBLP]
Worst case timing jitter and amplitude noise in differential signaling. [Citation Graph (, )][DBLP]
A PVT aware accurate statistical logic library for high- metal-gate nano-CMOS. [Citation Graph (, )][DBLP]
A general piece-wise nonlinear library modeling format and size reduction technique for gate-level timing, SI, power, and variation analysis. [Citation Graph (, )][DBLP]
Leakage optimization using transistor-level dual threshold voltage cell library. [Citation Graph (, )][DBLP]
An enhanced topology for reliability of a high performance 3.3V I/O buffer in a single-well bulk CMOS 1.8v-oxide low voltage process. [Citation Graph (, )][DBLP]
The design of a low-power high-speed current comparator in 0.35-m CMOS technology. [Citation Graph (, )][DBLP]
Comparison of supply noise and substrate noise reduction in SiGe BiCMOS and FDSOI processes. [Citation Graph (, )][DBLP]
An effective staggered-phase damping technique for suppressing power-gating resonance noise during mode transition. [Citation Graph (, )][DBLP]
Design and application of multimodal power gating structures. [Citation Graph (, )][DBLP]
Revisiting the linear programming framework for leakage power vs. performance optimization. [Citation Graph (, )][DBLP]
Parameter tuning in SVM-based power macro-modeling. [Citation Graph (, )][DBLP]
Performance-energy tradeoffs in reliable NoCs. [Citation Graph (, )][DBLP]
3D-GCP: An analytical model for the impact of process variations on the critical path delay distribution of 3D ICs. [Citation Graph (, )][DBLP]
Control of design specific variation in etch-assisted via pattern transfer by means of full-chip simulation. [Citation Graph (, )][DBLP]
New subthreshold concepts in 65nm CMOS technology. [Citation Graph (, )][DBLP]
On-chip transistor characterization arrays with digital interfaces for variability characterization. [Citation Graph (, )][DBLP]
Variability-aware optimization of nano-CMOS Active Pixel Sensors using design and analysis of Monte Carlo experiments. [Citation Graph (, )][DBLP]
Yield evaluation of analog placement with arbitrary capacitor ratio. [Citation Graph (, )][DBLP]
Analysis of performance and reliability trade-off in dummy pattern design for 32-nm technology. [Citation Graph (, )][DBLP]
A novel ACO-based pattern generation for peak power estimation in VLSI circuits. [Citation Graph (, )][DBLP]
Switch level optimization of digital CMOS gate networks. [Citation Graph (, )][DBLP]
hArtes design flow for heterogeneous platforms. [Citation Graph (, )][DBLP]
An efficient reliability evaluation approach for system-level design of embedded systems. [Citation Graph (, )][DBLP]
A case study on system-level modeling by aspect-oriented programming. [Citation Graph (, )][DBLP]
Performance evaluation of wireless networks on chip architectures. [Citation Graph (, )][DBLP]
Validating physical access layer of WiMAX using SystemVerilog. [Citation Graph (, )][DBLP]
Accelerating jitter tolerance qualification for high speed serial interfaces. [Citation Graph (, )][DBLP]
Improving the accuracy of rule-based equivalence checking of system-level design descriptions by identifying potential internal equivalences. [Citation Graph (, )][DBLP]
Efficient SAT-based techniques for Design of Experiments by using static variable ordering. [Citation Graph (, )][DBLP]
An abstraction mechanism to maximize stimulus portability across RTL, FPGA, software models and silicon of SoCs. [Citation Graph (, )][DBLP]
Timing yield estimation of digital circuits using a control variate technique. [Citation Graph (, )][DBLP]
A unified gate sizing formulation for optimizing soft error rate, cross-talk noise and power under process variations. [Citation Graph (, )][DBLP]
TuneLogic: Post-silicon tuning of dual-Vdd designs. [Citation Graph (, )][DBLP]
A case for exploiting complex arithmetic circuits towards performance yield enhancement. [Citation Graph (, )][DBLP]
A systematic approach to modeling and analysis of transient faults in logic circuits. [Citation Graph (, )][DBLP]
ESD event simulation automation using automatic extraction of the relevant portion of a full chip. [Citation Graph (, )][DBLP]
Parametric analysis to determine accurate interconnect extraction corners for design performance. [Citation Graph (, )][DBLP]
Exploratory study on circuit and architecture design of very high density diode-switch phase change memories. [Citation Graph (, )][DBLP]
Adaptive voltage controlled nanoelectronic addressing for yield, accuracy and resolution. [Citation Graph (, )][DBLP]
Defect characterization in magnetic field coupled arrays. [Citation Graph (, )][DBLP]
CAD utilities to comprehend layout-dependent stress effects in 45 nm high- performance SOI custom macro design. [Citation Graph (, )][DBLP]
A 1.2 volt, 90nm, 16-bit three way segmented digital to analog converter (DAC) for low power applications. [Citation Graph (, )][DBLP]
Design methodology of high performance on-chip global interconnect using terminated transmission-line. [Citation Graph (, )][DBLP]
New word-line driving scheme for suppressing oxide-tunneling leakage in sub-65-nm SRAMs. [Citation Graph (, )][DBLP]
Adaptive leakage control on body biasing for reducing power consumption in CMOS VLSI circuit. [Citation Graph (, )][DBLP]
Standby power reduction and SRAM cell optimization for 65nm technology. [Citation Graph (, )][DBLP]
Optimization strategies to improve statistical timing. [Citation Graph (, )][DBLP]
Clock gating effectiveness metrics: Applications to power optimization. [Citation Graph (, )][DBLP]
Buffer/flip-flop block planning for power-integrity-driven floorplanning. [Citation Graph (, )][DBLP]
On temperature planarization effect of copper dummy fills in deep nanometer technology. [Citation Graph (, )][DBLP]
Fast characterization of parameterized cell library. [Citation Graph (, )][DBLP]
Cell shifting aware of wirelength and overlap. [Citation Graph (, )][DBLP]
Lagrangian relaxation based register placement for high-performance circuits. [Citation Graph (, )][DBLP]
Implementation of power managed hyper transport system for transmission of HD video. [Citation Graph (, )][DBLP]
Power aware placement for FPGAs with dual supply voltages. [Citation Graph (, )][DBLP]
VLSI architectures of perceptual based video watermarking for real-time copyright protection. [Citation Graph (, )][DBLP]
VeriC: A semi-hardware description language to bridge the gap between ESL design and RTL models. [Citation Graph (, )][DBLP]
Power estimation methodology for a high-level synthesis framework. [Citation Graph (, )][DBLP]
Variability aware modeling of SoCs: From device variations to manufactured system yield. [Citation Graph (, )][DBLP]
Kriging Model combined with latin hypercube sampling for surrogate modeling of analog integrated circuit performance. [Citation Graph (, )][DBLP]
Retrospective on electronics technology and prospective methods for co-design of IC packaging and manufacturing improvements. [Citation Graph (, )][DBLP]
50GB/s signaling on organic substrates using PMTL technology. [Citation Graph (, )][DBLP]
Die/wafer stacking with reciprocal design symmetry (RDS) for mask reuse in three-dimensional (3D) integration technology. [Citation Graph (, )][DBLP]
Parallel flow to analyze the impact of the voltage regulator model in nanoscale power distribution network. [Citation Graph (, )][DBLP]
An analytic model for Ge/Si core/shell nanowire MOSFETs considering drift-diffusion and ballistic transport. [Citation Graph (, )][DBLP]
Zero clock skew synchronization with rotary clocking technology. [Citation Graph (, )][DBLP]
Place and route considerations for voltage interpolated designs. [Citation Graph (, )][DBLP]
Crosstalk pessimism reduction with path base analysis. [Citation Graph (, )][DBLP]
The impact of BEOL lithography effects on the SRAM cell performance and yield. [Citation Graph (, )][DBLP]
Process variation impact on FPGA configuration memory. [Citation Graph (, )][DBLP]
Efficient statistical analysis of read timing failures in SRAM circuits. [Citation Graph (, )][DBLP]
Increasing memory yield in future technologies through innovative design. [Citation Graph (, )][DBLP]
An efficient current-based logic cell model for crosstalk delay analysis. [Citation Graph (, )][DBLP]
An application-specific adjoint sensitivity analysis framework for clock mesh sensitivity computation. [Citation Graph (, )][DBLP]
Early clock prototyping for design analysis and quality entitlement. [Citation Graph (, )][DBLP]
A study of decoupling capacitor effectiveness in power and ground grid networks. [Citation Graph (, )][DBLP]
A 0.56-V 128kb 10T SRAM using column line assist (CLA) scheme. [Citation Graph (, )][DBLP]
Design and implementation of a sub-threshold BFSK transmitter. [Citation Graph (, )][DBLP]
A universal level converter towards the realization of energy efficient implantable drug delivery Nano-Electro-Mechanical-Systems. [Citation Graph (, )][DBLP]
Temperature effects on energy optimization in sub-threshold circuit design. [Citation Graph (, )][DBLP]
Charge recovery logic as a side channel attack countermeasure. [Citation Graph (, )][DBLP]
Impact of SoC power management techniques on verification and testing. [Citation Graph (, )][DBLP]
A study on impact of loading effect on capacitive crosstalk noise. [Citation Graph (, )][DBLP]
Simultaneous test pattern compaction, ordering and X-filling for testing power reduction. [Citation Graph (, )][DBLP]
Markov source based test length optimized SCAN-BIST architecture. [Citation Graph (, )][DBLP]
Calculation of stress probability for NBTI-aware timing analysis. [Citation Graph (, )][DBLP]
Derating for static timing analysis: Theory and practice. [Citation Graph (, )][DBLP]
An information theoretic framework to compute the MAX/MIN operations in parameterized statistical timing analysis. [Citation Graph (, )][DBLP]
A generalized V-shaped multilevel method for large scale floorplanning. [Citation Graph (, )][DBLP]
Simultaneous buffer and interlayer via planning for 3D floorplanning. [Citation Graph (, )][DBLP]
IR-drop management CAD techniques in FPGAs for power grid reliability. [Citation Graph (, )][DBLP]
Functionally valid gate-level peak power estimation for processors. [Citation Graph (, )][DBLP]
On-chip DC-DC converters for three-dimensional ICs. [Citation Graph (, )][DBLP]
Active decap design considerations for optimal supply noise reduction. [Citation Graph (, )][DBLP]
Efficient power network analysis with complete inductive modeling. [Citation Graph (, )][DBLP]
Parallel partitioning based on-chip power distribution network analysis using locality acceleration. [Citation Graph (, )][DBLP]
SRAM supply voltage scaling: A reliability perspective. [Citation Graph (, )][DBLP]
Low power adaptive pipeline based on instruction isolation. [Citation Graph (, )][DBLP]
Post-Silicon Clock-nvert (PSCI) for reducing process-variation induced skew in buffered clock networks. [Citation Graph (, )][DBLP]
Variation-tolerant hierarchical voltage monitoring circuit for soft error detection. [Citation Graph (, )][DBLP]
