Conferences in DBLP

International Conference on Formal Methods and Models for Co-Design (memocode)
2008 (conf/memocode/2008)

1. 
   Arithmetic Circuits Verification without Looking for Internal Equivalences. [Citation Graph (, )][DBLP]
   
   
2. 
   From Data to Events: Checking Properties on the Control of a System. [Citation Graph (, )][DBLP]
   
   
3. 
   Vacuity Analysis by Fault Simulation. [Citation Graph (, )][DBLP]
   
   
4. 
   Rule-Based Approaches for Equivalence Checking of SpecC Programs. [Citation Graph (, )][DBLP]
   
   
5. 
   Static Deadlock Detection for the SHIM Concurrent Language. [Citation Graph (, )][DBLP]
   
   
6. 
   A Comparison of Two SystemC/TLM Semantics for Formal Verification. [Citation Graph (, )][DBLP]
   
   
7. 
   Latency-Insensitive Hardware/Software Interfaces. [Citation Graph (, )][DBLP]
   
   
8. 
   Bisimulator 2.0: An On-the-Fly Equivalence Checker based on Boolean Equation Systems. [Citation Graph (, )][DBLP]
   
   
9. 
   Assertion-Based Design with Horus. [Citation Graph (, )][DBLP]
   
   
10. 
    A System Verilog Rewriting System for RTL Abstraction with Pentium Case Study. [Citation Graph (, )][DBLP]
    
    
11. 
    Directed-Logical Testing for Functional Verification of Microprocessors. [Citation Graph (, )][DBLP]
    
    
12. 
    Estimating the Performance of Cache Replacement Policies. [Citation Graph (, )][DBLP]
    
    
13. 
    Classification of General Data Flow Actors into Known Models of Computation. [Citation Graph (, )][DBLP]
    
    
14. 
    On the Deterministic Multi-threaded Software Synthesis from Polychronous Specifications. [Citation Graph (, )][DBLP]
    
    
15. 
    Virtual prototyping AADL architectures in a polychronous model of computation. [Citation Graph (, )][DBLP]
    
    
16. 
    MEMOCODE 2008 Co-Design Contest. [Citation Graph (, )][DBLP]
    
    
17. 
    High-throughput Pipelined Mergesort. [Citation Graph (, )][DBLP]
    
    
18. 
    Hardware Accelerated Crypto Merge Sort: MEMOCODE 2008 Design Contest. [Citation Graph (, )][DBLP]
    
    
19. 
    H.264 Decoder: A Case Study in Multiple Design Points. [Citation Graph (, )][DBLP]
    
    
20. 
    Correctness of a Fault-Tolerant Real-Time Scheduler and its Hardware Implementation. [Citation Graph (, )][DBLP]
    
    
21. 
    Specification and Verification of LambdaRAM: A Wide-area Distributed Cache for High Performance Computing. [Citation Graph (, )][DBLP]
    
    
22. 
    Hands-on Introduction to Bluespec System Verilog (BSV) (Abstract). [Citation Graph (, )][DBLP]