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Conferences in DBLP
Optimizing NUCA Organizations and Wiring Alternatives for Large Caches with CACTI 6.0. [Citation Graph (, )][DBLP]
Process Variation Tolerant 3T1D-Based Cache Architectures. [Citation Graph (, )][DBLP]
Mitigating Parameter Variation with Dynamic Fine-Grain Body Biasing. [Citation Graph (, )][DBLP]
Optimal versus Heuristic Global Code Scheduling. [Citation Graph (, )][DBLP]
Global Multi-Threaded Instruction Scheduling. [Citation Graph (, )][DBLP]
Revisiting the Sequential Programming Model for Multi-Core. [Citation Graph (, )][DBLP]
Penelope: The NBTI-Aware Processor. [Citation Graph (, )][DBLP]
Software-Based Online Detection of Hardware Defects Mechanisms, Architectural Support, and Evaluation. [Citation Graph (, )][DBLP]
Self-calibrating Online Wearout Detection. [Citation Graph (, )][DBLP]
Implementing Signatures for Transactional Memory. [Citation Graph (, )][DBLP]
Smart Refresh: An Enhanced Memory Controller Design for Reducing Energy in Conventional and 3D Die-Stacked DRAMs. [Citation Graph (, )][DBLP]
Stall-Time Fair Memory Access Scheduling for Chip Multiprocessors. [Citation Graph (, )][DBLP]
Impact of Cache Coherence Protocols on the Processing of Network Traffic. [Citation Graph (, )][DBLP]
Flattened Butterfly Topology for On-Chip Networks. [Citation Graph (, )][DBLP]
Using Address Independent Seed Encryption and Bonsai Merkle Trees to Make Secure Processors OS- and Performance-Friendly. [Citation Graph (, )][DBLP]
Multi-bit Error Tolerant Caches Using Two-Dimensional Error Coding. [Citation Graph (, )][DBLP]
Argus: Low-Cost, Comprehensive Error Detection in Simple Cores. [Citation Graph (, )][DBLP]
Leveraging 3D Technology for Improved Reliability. [Citation Graph (, )][DBLP]
Effective Optimistic-Checker Tandem Core Design through Architectural Pruning. [Citation Graph (, )][DBLP]
FPGA-Accelerated Simulation Technologies (FAST): Fast, Full-System, Cycle-Accurate Simulators. [Citation Graph (, )][DBLP]
Microarchitectural Design Space Exploration Using an Architecture-Centric Approach. [Citation Graph (, )][DBLP]
Informed Microarchitecture Design Space Exploration Using Workload Dynamics. [Citation Graph (, )][DBLP]
Time Interpolation: So Many Metrics, So Few Registers. [Citation Graph (, )][DBLP]
Low-Cost Epoch-Based Correlation Prefetching for Commercial Applications. [Citation Graph (, )][DBLP]
A Framework for Coarse-Grain Optimizations in the On-Chip Memory Hierarchy. [Citation Graph (, )][DBLP]
Uncorq: Unconstrained Snoop Request Delivery in Embedded-Ring Multiprocessors. [Citation Graph (, )][DBLP]
A Framework for Providing Quality of Service in Chip Multi-Processors. [Citation Graph (, )][DBLP]
A Practical Approach to Exploiting Coarse-Grained Pipeline Parallelism in C Programs. [Citation Graph (, )][DBLP]
Data Access Partitioning for Fine-grain Parallelism on Multicore Architectures. [Citation Graph (, )][DBLP]
Composable Lightweight Processors. [Citation Graph (, )][DBLP]
The Art of Deception: Adaptive Precision Reduction for Area Efficient Physics Acceleration. [Citation Graph (, )][DBLP]
Dynamic Warp Formation and Scheduling for Efficient GPU Control Flow. [Citation Graph (, )][DBLP]
Scavenger: A New Last Level Cache Architecture with Global Block Priority. [Citation Graph (, )][DBLP]
Guaranteeing Hits to Improve the Efficiency of a Small Instruction Cache. [Citation Graph (, )][DBLP]
Emulating Optimal Replacement with a Shepherd Cache. [Citation Graph (, )][DBLP]
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