Conferences in DBLP
Multi-level Parallelism in the Computational Modeling of the Heart. [Citation Graph (, )][DBLP ] Computational Characteristics of Production Seismic Migration and its Performance on Novel Processor Architectures. [Citation Graph (, )][DBLP ] Voice Command Recognition with Dynamic Time Warping (DTW) using Graphics Processing Units (GPU) with Compute Unified Device Architecture (CUDA). [Citation Graph (, )][DBLP ] Exploring Novel Parallelization Technologies for 3-D Imaging Applications. [Citation Graph (, )][DBLP ] Low-cost Techniques for Reducing Branch Context Pollution in a Soft Realtime Embedded Multithreaded Processor. [Citation Graph (, )][DBLP ] Self-Imposed Temporal Redundancy: An Efficient Technique to Enhance the Reliability of Pipelined Functional Units. [Citation Graph (, )][DBLP ] Predicting Loop Termination to Boost Speculative Thread-Level Parallelism in Embedded Applications. [Citation Graph (, )][DBLP ] Multi2Sim: A Simulation Framework to Evaluate Multicore-Multithreaded Processors. [Citation Graph (, )][DBLP ] Performance Improvement of the Parallel Lattice Boltzmann Method Through Blocked Data Distributions. [Citation Graph (, )][DBLP ] A Scalable Parallel Deduplication Algorithm. [Citation Graph (, )][DBLP ] A Multigrid-Schwarz Method for the Solution of Hydrodynamics and Heat Transfer Problems in Unstructured Meshes. [Citation Graph (, )][DBLP ] Performance Evaluation of the Dual-Core Based SGI Altix 4700. [Citation Graph (, )][DBLP ] Impacts of Multiprocessor Configurations on Workloads in Bioinformatics. [Citation Graph (, )][DBLP ] Efficient Hardware for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning. [Citation Graph (, )][DBLP ] Optimized Math Functions for a Fixed-Point DSP Architecture. [Citation Graph (, )][DBLP ] A Component-Oriented Support for Hierarchical MPI Programming on Multi-Cluster Grid Environments. [Citation Graph (, )][DBLP ] A Selector of Grid Resources based on the Semantic Integration of Multiple Ontologies. [Citation Graph (, )][DBLP ] A Novel Algorithm for Indirect Reputation-Based Grid Resource Management. [Citation Graph (, )][DBLP ] Register File Energy Optimization for Snooping Based Clustered VLIW Architectures. [Citation Graph (, )][DBLP ] Queue Register File Optimization Algorithm for QueueCore Processor. [Citation Graph (, )][DBLP ] An Intelligent Mechanism to Explore a Two-Level Cache Hierarchy Considering Energy Consumption and Time Performance. [Citation Graph (, )][DBLP ] A Code Compression Method to Cope with Security Hardware Overheads. [Citation Graph (, )][DBLP ] Architectural Breakdown of End-to-End Latency in a TCP/IP Network. [Citation Graph (, )][DBLP ] Performance Analysis and Linear Optimization Modeling of All-to-all Collective Communication Algorithms. [Citation Graph (, )][DBLP ] Design of a Feasible On-Chip Interconnection Network for a Chip Multiprocessor (CMP). [Citation Graph (, )][DBLP ] Node Level Primitives for Parallel Exact Inference. [Citation Graph (, )][DBLP ] Fault-tolerance in filter-labeled-stream applications. [Citation Graph (, )][DBLP ] High-Level Service Connectors for Component-Based High Performance Computing. [Citation Graph (, )][DBLP ] On-line Scheduling of MPI-2 Programs with Hierarchical Work Stealing. [Citation Graph (, )][DBLP ] Exigency-based real-time scheduling policy to provide absolute QoS for web services. [Citation Graph (, )][DBLP ] DTA-C: A Decoupled multi-Threaded Architecture for CMP Systems. [Citation Graph (, )][DBLP ] Automatic Constraint Partitioning to Speed Up CLP Execution. [Citation Graph (, )][DBLP ] 