Conferences in DBLP

(nocs)
2009 (conf/nocs/2009)

1. 
   Keynote 1 NoCs: It is about the memory and the programming model. [Citation Graph (, )][DBLP]
   
   
2. 
   HiRA: A methodology for deadlock free routing in hierarchical networks on chip. [Citation Graph (, )][DBLP]
   
   
3. 
   Using adaptive routing to compensate for performance heterogeneity. [Citation Graph (, )][DBLP]
   
   
4. 
   Fault-tolerant architecture and deflection routing for degradable NoC switches. [Citation Graph (, )][DBLP]
   
   
5. 
   Adaptive stochastic routing in fault-tolerant on-chip networks. [Citation Graph (, )][DBLP]
   
   
6. 
   Static virtual channel allocation in oblivious routing. [Citation Graph (, )][DBLP]
   
   
7. 
   Analysis of worst-case delay bounds for best-effort communication in wormhole networks on chip. [Citation Graph (, )][DBLP]
   
   
8. 
   Lookahead-based adaptive voltage scheme for energy-efficient on-chip interconnect links. [Citation Graph (, )][DBLP]
   
   
9. 
   Recursive partitioning multicast: A bandwidth-efficient routing for Networks-on-Chip. [Citation Graph (, )][DBLP]
   
   
10. 
    Analytical modeling and evaluation of On-Chip Interconnects using Network Calculus. [Citation Graph (, )][DBLP]
    
    
11. 
    Energy efficient application mapping to NoC processing elements operating at multiple voltage levels. [Citation Graph (, )][DBLP]
    
    
12. 
    The design of a latency constrained, power optimized NoC for a 4G SoC. [Citation Graph (, )][DBLP]
    
    
13. 
    Performance Evaluation of NoC Architectures for Parallel Workloads. [Citation Graph (, )][DBLP]
    
    
14. 
    Packet-level static timing analysis for NoCs. [Citation Graph (, )][DBLP]
    
    
15. 
    Increasing NoC power estimation accuracy through a rate-based model. [Citation Graph (, )][DBLP]
    
    
16. 
    On-Chip photonic interconnects for scalable multi-core architectures. [Citation Graph (, )][DBLP]
    
    
17. 
    A Modeling and exploration framework for interconnect network design in the nanometer era. [Citation Graph (, )][DBLP]
    
    
18. 
    Power reduction through physical placement of asynchronous routers. [Citation Graph (, )][DBLP]
    
    
19. 
    Networks-on-chip in emerging interconnect paradigms: Advantages and challenges. [Citation Graph (, )][DBLP]
    
    
20. 
    Keynote 2 NoC's at the center of chip architecture: Urgent needs (today) and what they must become (future). [Citation Graph (, )][DBLP]
    
    
21. 
    Analysis of photonic networks for a chip multiprocessor using scientific applications. [Citation Graph (, )][DBLP]
    
    
22. 
    Scalability of network-on-chip communication architecture for 3-D meshes. [Citation Graph (, )][DBLP]
    
    
23. 
    Silicon-photonic clos networks for global on-chip communication. [Citation Graph (, )][DBLP]
    
    
24. 
    Contention-free on-chip routing of optical packets. [Citation Graph (, )][DBLP]
    
    
25. 
    Connection-centric network for spiking neural networks. [Citation Graph (, )][DBLP]
    
    
26. 
    A Communication and configuration controller for NoC based reconfigurable data flow architecture. [Citation Graph (, )][DBLP]
    
    
27. 
    Configurable emulated shared memory architecture for general purpose MP-SOCs and NOC regions. [Citation Graph (, )][DBLP]
    
    
28. 
    Best of both worlds: A bus enhanced NoC (BENoC). [Citation Graph (, )][DBLP]
    
    
29. 
    Flow-aware allocation for on-chip networks. [Citation Graph (, )][DBLP]
    
    
30. 
    CTC: An end-to-end flow control protocol for multi-core systems-on-chip. [Citation Graph (, )][DBLP]
    
    
31. 
    Performance and power efficient on-chip communication using adaptive virtual point-to-point connections. [Citation Graph (, )][DBLP]
    
    
32. 
    Keynote 3 (Banquet Talk) Digital space. [Citation Graph (, )][DBLP]
    
    
33. 
    A GALS many-core heterogeneous DSP platform with source-synchronous on-chip interconnection network. [Citation Graph (, )][DBLP]
    
    
34. 
    A modular synchronizing FIFO for NoCs. [Citation Graph (, )][DBLP]
    
    
35. 
    Estimating reliability and throughput of source-synchronous wave-pipelined interconnect. [Citation Graph (, )][DBLP]
    
    
36. 
    Comparing tightly and loosely coupled mesochronous synchronizers in a NoC switch architecture. [Citation Graph (, )][DBLP]
    
    
37. 
    Dynamic packet fragmentation for increased virtual channel utilization in on-chip routers. [Citation Graph (, )][DBLP]
    
    
38. 
    Diagnosis of interconnect shorts in mesh NoCs. [Citation Graph (, )][DBLP]
    
    
39. 
    BiNoC: A bidirectional NoC architecture with dynamic self-reconfigurable channel. [Citation Graph (, )][DBLP]
    
    
40. 
    Exploring concentration and channel slicing in on-chip network router. [Citation Graph (, )][DBLP]
    
    
41. 
    Author index. [Citation Graph (, )][DBLP]