Synchronization for an optimal real-time scheduling algorithm on multiprocessors. [Citation Graph (, )][DBLP]
Augmenting sensitivity analysis for embedded applications by program level derivation of process parameters. [Citation Graph (, )][DBLP]
Improving the Worst-Case Execution Time Accuracy by Inter-Task Instruction Cache Analysis. [Citation Graph (, )][DBLP]
Real-time characteristics of Switched Ethernet for "1553B"-Embedded Applications: Simulation and Analysis. [Citation Graph (, )][DBLP]
Protocols for Active RFID - The Energy Consumption Aspect. [Citation Graph (, )][DBLP]
A Real-Time Interface for Agent-Based Control. [Citation Graph (, )][DBLP]
Optimized Resource Dimensioning in an embedded CAN-CAN Gateway. [Citation Graph (, )][DBLP]
A Formal Framework for the Correct-by-construction and Verification of Distributed Time Triggered Systems. [Citation Graph (, )][DBLP]
Optimization of Memory-Constrained Hybrid BIST for Testing Core-Based Systems. [Citation Graph (, )][DBLP]
The Effect of Hardware Platform Selection on Safety-Critical Software in Embedded Systems: Empirical Evaluations. [Citation Graph (, )][DBLP]
Energy and Performance Trade-offs between Instruction Reuse and Trivial Computations for Embedded Applications. [Citation Graph (, )][DBLP]
Performance and Memory Profiling for Embedded System Design. [Citation Graph (, )][DBLP]
A Timed Multitasking Architecture for Distributed Embedded Systems. [Citation Graph (, )][DBLP]
Shared Data Analysis for Multi-Tasking Real-Time System Testing. [Citation Graph (, )][DBLP]
An Open Framework for Detailed Hardware Modeling. [Citation Graph (, )][DBLP]
Design Space Exploration with Evolutionary Multi-Objective Optimisation. [Citation Graph (, )][DBLP]
Novel Genome Coding of Genetic Algorithms for the System Partitioning Problem. [Citation Graph (, )][DBLP]
Image-based Control of an Autonomous Robot with Omnidirectional Vision. [Citation Graph (, )][DBLP]
An FPGA Implementation for a Kalman Filter with Application to Mobile Robotics. [Citation Graph (, )][DBLP]
Deadline-Aware Scheduling Policies for Bluetooth Networks in Industrial Communications. [Citation Graph (, )][DBLP]
Analysis of the IEEE 802.15.4 Standard for a Wireless Closed Loop Control System for Heavy Duty Cranes. [Citation Graph (, )][DBLP]
Modification of Field Bus Telegrams for Hybrid Commissioning; Merge-Tool for PROFIBUS. [Citation Graph (, )][DBLP]
Mapping a Pipelined Data Path onto a Network-on-Chip. [Citation Graph (, )][DBLP]
A System-on-Chip Implementation for Modular Exponentiation Using the Sliding-Window Method with Variable-Length Partitioning. [Citation Graph (, )][DBLP]
A Dynamically Partial-reconfigurable FPGA-based Architecture for Data Processing on Space Solar Telescope. [Citation Graph (, )][DBLP]
Refactoring an Automotive Embedded Software Stack using the Component-Based Paradigm. [Citation Graph (, )][DBLP]
Applying Model Checking to an Automotive Microcontroller Application. [Citation Graph (, )][DBLP]
Coexistence of Time-Triggered and Event-Triggered Traffic in Switched Full-Duplex Ethernet Networks. [Citation Graph (, )][DBLP]
Adequacy between AUTOSAR OS specification and real-time scheduling theory. [Citation Graph (, )][DBLP]
A multiform time approach to real-time system modeling; Application to an automotive system. [Citation Graph (, )][DBLP]
Distinguishing Environment and System in Coloured Petri Net Models of Reactive Systems. [Citation Graph (, )][DBLP]
A Formal Description Technique for Interactive Cockpit Applications Compliant with ARINC Specification 661. [Citation Graph (, )][DBLP]
Protocol Modelling Semantics for Embedded Systems. [Citation Graph (, )][DBLP]
Translating Synchronous Petri Nets into PROMELA for Verifying Behavioural Properties. [Citation Graph (, )][DBLP]
Process State Machines for Behavioral Modeling of Embedded Systems. [Citation Graph (, )][DBLP]
Experience with integration and certification of COTS based embedded system into advanced avionics system. [Citation Graph (, )][DBLP]
Testing of a 32-bit High Performance Embedded Microprocessor. [Citation Graph (, )][DBLP]
Minimizing Latency and Data Memory Requirement for Real-time Chain-Structured Synchronous Dataflow. [Citation Graph (, )][DBLP]