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Conferences in DBLP
(socc)
2008 (conf/socc/2008)
"SOC challenges in the terabit networks era". [Citation Graph (, )][DBLP]
"Future trends in PC computing and their implications to SoC". [Citation Graph (, )][DBLP]
"Surfing the iSoC multitechnology platform: Volumetric growth beyond Moore's law". [Citation Graph (, )][DBLP]
Energy-optimal signaling and ordering of bits for area-constrained interconnects. [Citation Graph (, )][DBLP]
A unified power measurement and management platform for pipelined MPSoC executions. [Citation Graph (, )][DBLP]
Partitioned reuse cache for energy-efficient soft-error protection of functional units. [Citation Graph (, )][DBLP]
The role of interconnects in the performance scalability of multicore architectures. [Citation Graph (, )][DBLP]
ILP-based scheme for timing variation-aware scheduling and resource binding. [Citation Graph (, )][DBLP]
Exploiting loop-level parallelism on multi-core architectures for the wimax physical layer. [Citation Graph (, )][DBLP]
Extensible software emulator for reconfigurable instruction cell based processors. [Citation Graph (, )][DBLP]
MRPSIM: A TLM based simulation tool for MPSOCS targeting dynamically reconfigurable processors. [Citation Graph (, )][DBLP]
Pseudo-random clocking to enhance signal integrity. [Citation Graph (, )][DBLP]
Nanoscale on-chip decoupling capacitors. [Citation Graph (, )][DBLP]
Built-in functional tests for fast validation of a 40Gbps coherent optical receiver SoC ASIC. [Citation Graph (, )][DBLP]
A multi-wire error correction scheme for reliable and energy efficient SOC links using hamming product codes. [Citation Graph (, )][DBLP]
Fluidity concept for NoC: A congestion avoidance and relief routing scheme. [Citation Graph (, )][DBLP]
Configurable error correction for multi-wire errors in switch-to-switch SOC links. [Citation Graph (, )][DBLP]
Guaranteeing QoS with the pipelined multi-channel central caching NoC communication architecture. [Citation Graph (, )][DBLP]
Energy minimization using a greedy randomized heuristic for the voltage assignment problem in NoC. [Citation Graph (, )][DBLP]
Composability in the time-triggered system-on-chip architecture. [Citation Graph (, )][DBLP]
A systematic approach to synthesis of verification test-suites for modular SoC designs. [Citation Graph (, )][DBLP]
A 300-mV 36-muW multiphase dual digital clock output generator with self-calibration. [Citation Graph (, )][DBLP]
A resistance deviation-to-time interval converter for resistive sensors. [Citation Graph (, )][DBLP]
Design methodolgy for HD Photo compression algorithm targeting a FPGA. [Citation Graph (, )][DBLP]
Design of low flicker noise active CMOS mixer. [Citation Graph (, )][DBLP]
65NM sub-threshold 11T-SRAM for ultra low voltage applications. [Citation Graph (, )][DBLP]
Evaluation of contrast limited adaptive histogram equalization (CLAHE) enhancement on a FPGA. [Citation Graph (, )][DBLP]
Novel start-up circuit with enhanced power-up characteristic for bandgap references. [Citation Graph (, )][DBLP]
Unification of obstacle-avoiding rectilinear Steiner tree construction. [Citation Graph (, )][DBLP]
Analysis of retention time under multi-configuration on a DORGA. [Citation Graph (, )][DBLP]
Performance evaluation of a FFT using adpative clocking. [Citation Graph (, )][DBLP]
A comparator-based switched-capacitor integrator using a new charge control circuit. [Citation Graph (, )][DBLP]
Area efficient delay-insensitive and differential current sensing on-chip interconnect. [Citation Graph (, )][DBLP]
Temperature measurement in Content Addressable Memory cells using bias-controlled VCO. [Citation Graph (, )][DBLP]
A coarse-grained Dynamically Reconfigurable MAC Processor for power-sensitive multi-standard devices. [Citation Graph (, )][DBLP]
A multi-mode sphere detector architecture for WLAN applications. [Citation Graph (, )][DBLP]
Slack redistribution in pipelined circuits for enhanced soft-error rate reduction. [Citation Graph (, )][DBLP]
Application development flow for on-chip distributed architectures. [Citation Graph (, )][DBLP]
A novel 0.6V CMOS folded Gilbert-cell mixer for UWB applications. [Citation Graph (, )][DBLP]
A robust ultra-low power asynchronous FIFO memory with self-adaptive power control. [Citation Graph (, )][DBLP]
A low power and low area active clock deskewing technique for sub-90nm technologies. [Citation Graph (, )][DBLP]
A low power 32 nanometer CMOS digitally controlled oscillator. [Citation Graph (, )][DBLP]
Pseudo parallel architecture for AES with error correction. [Citation Graph (, )][DBLP]
Implementing high definition video codec on TI DM6467 SOC. [Citation Graph (, )][DBLP]
A novel 5.46 mW H.264/AVC video stream parser IC. [Citation Graph (, )][DBLP]
A low-power design of quantization for H.264 video coding standard. [Citation Graph (, )][DBLP]
Speed control for a hardware based H.264/AVC encoder. [Citation Graph (, )][DBLP]
Power optimization for FinFET-based circuits using genetic algorithms. [Citation Graph (, )][DBLP]
In-situ self-aware adaptive power control system with multi-mode power gating network. [Citation Graph (, )][DBLP]
Supply voltage selection in Voltage Island based SoC design. [Citation Graph (, )][DBLP]
A multi-standard micro-programmable deblocking filter architecture and its application to VC-1 video decoder. [Citation Graph (, )][DBLP]
Multi-standard sub-pixel interpolation architecture for video Motion Estimation. [Citation Graph (, )][DBLP]
An efficient lossless embedded compression engine using compacted-FELICS algorithm. [Citation Graph (, )][DBLP]
Low-power floating bitline 8-T SRAM design with write assistant circuits. [Citation Graph (, )][DBLP]
A subthreshold single ended I/O SRAM cell design for nanometer CMOS technologies. [Citation Graph (, )][DBLP]
Low power 8T SRAM using 32nm independent gate FinFET technology. [Citation Graph (, )][DBLP]
Failure analysis for ultra low power nano-CMOS SRAM under process variations. [Citation Graph (, )][DBLP]
1.5V 0.5mW 2MSPS 10B DAC with rail-to-rail output in 0.13mum CMOS technology. [Citation Graph (, )][DBLP]
Statistical averaging based linearity optimization for resistor string DAC architectures in nanoscale processes. [Citation Graph (, )][DBLP]
A higher-order mismatch-shaping method for multi-bit Sigma-Delta Modulators. [Citation Graph (, )][DBLP]
A low power sub-1 V CMOS voltage reference. [Citation Graph (, )][DBLP]
Design space exploration for application specific FPGAS in system-on-a-chip designs. [Citation Graph (, )][DBLP]
A framework of architectural synthesis for dynamically reconfigurable FPGAs. [Citation Graph (, )][DBLP]
Reconfiguralbe multimedia accelerator for mobile systems. [Citation Graph (, )][DBLP]
Energy consumption reduction mechanism by tuning cache configuration usign NIOS II processor. [Citation Graph (, )][DBLP]
VLSI passive switched capacitor signal processing circuits: Circuit architecture, closed form modeling and applications. [Citation Graph (, )][DBLP]
A novel CMOS exponential approximation circuit. [Citation Graph (, )][DBLP]
3-D Heterogeneous SoC for detecting and filtering infected biological cells. [Citation Graph (, )][DBLP]
Novel mixed domain VLSI signal processing circuits for high performance, low power and area penalty SOC signal processing. [Citation Graph (, )][DBLP]
Design of a baseband processor for software radio using FPGAs. [Citation Graph (, )][DBLP]
OFDM symbol timing synchronization system on a Reconfigurable Instruction Cell Array. [Citation Graph (, )][DBLP]
Reconfigurable flash A/D converters. [Citation Graph (, )][DBLP]
Programmable all-digital adaptive deskewing and phase shifting. [Citation Graph (, )][DBLP]
A 6-Gbit/s SATA spread-spectrum clock generator using two-stage delta-sigma modulator. [Citation Graph (, )][DBLP]
A spread spectrum clock generator using digital modulation scheme. [Citation Graph (, )][DBLP]
All digital time-to-digital converter using single delay-locked loop. [Citation Graph (, )][DBLP]
New low voltage, high PSRR, CMOS bandgap voltage reference. [Citation Graph (, )][DBLP]
A timing methodology considering within-die clock skew variations. [Citation Graph (, )][DBLP]
X-clock routing based on pattern matching. [Citation Graph (, )][DBLP]
An automated design method for chip power distribution. [Citation Graph (, )][DBLP]
A low-power 1-Gbps reconfigurable LDPC decoder design for multiple 4G wireless standards. [Citation Graph (, )][DBLP]
High performance IP lookup circuit using DDR SDRAM. [Citation Graph (, )][DBLP]
Power/throughput/area efficient PIM-based reconfigurable array for parallel processing. [Citation Graph (, )][DBLP]
A Discrepancy-Computationless RiBM algorithm and its architecture for BCH decoders. [Citation Graph (, )][DBLP]
Design and verification of complex SoC with configurable, extensible processors. [Citation Graph (, )][DBLP]
A new generation of C-base synthesis tool and domain-specific computing. [Citation Graph (, )][DBLP]
Low power design under parameter variations. [Citation Graph (, )][DBLP]
Real-time implementation of H.264 Video Coding. [Citation Graph (, )][DBLP]
Asynchronous circuit design using Handshake Solutions. [Citation Graph (, )][DBLP]
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