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Conferences in DBLP
(sips)
2006 (conf/sips/2006)
Molecular quantum-dot cellular automata. [Citation Graph (, )][DBLP]
Signal Processing Based Implantable Microsystems for Intracortical Therapeutic Purposes. [Citation Graph (, )][DBLP]
Design of high performance timing recovery loops for communication applications. [Citation Graph (, )][DBLP]
Automating the Verification of SDR Base band Signal Processing Algorithms Developed on DSP/FPGA Platform. [Citation Graph (, )][DBLP]
Configuration and Representation of Large-Scale Dataflow Graphs using the Dataflow Interchange Format. [Citation Graph (, )][DBLP]
Exploit Multiple-Domain Sparseness for HSDPA Chip Level Equalization in SDR: Algorithm and DSP Implementation. [Citation Graph (, )][DBLP]
Design and Implementation of Turbo Decoders for Software Defined Radio. [Citation Graph (, )][DBLP]
Low Complexity List Updating Circuits for List Sphere Decoders. [Citation Graph (, )][DBLP]
Performance Analysis of a New Transmission Scheme for Multi-Relay Channels. [Citation Graph (, )][DBLP]
A Reconfigurable SOS-based Rayleigh Fading Channel Simulator. [Citation Graph (, )][DBLP]
Low complexity iterative joint detection, decoding, and channel estimation for wireless MIMO system. [Citation Graph (, )][DBLP]
Maximum Likelihood Estimation of Carrier Frequency Offset in Correlated MIMO OFDM Systems. [Citation Graph (, )][DBLP]
Reduced-Complexity Pipelined Architectures for Finite Field Inversions. [Citation Graph (, )][DBLP]
Rapid IP Design of Variable-length Cached-FFT Processor for OFDM-based Communication Systems. [Citation Graph (, )][DBLP]
A Structural Study and Hyperedge Clustering Technique for Large Scale Circuits. [Citation Graph (, )][DBLP]
Performance Evaluation of an SIMD Architecture with a Multi-bank Vector Memory Unit. [Citation Graph (, )][DBLP]
Digit-Serial Systolic Architectures for Inversions over GF(2m). [Citation Graph (, )][DBLP]
A Reduced-Complexity, Scalable Implementation of Low Density Parity Check (LDPC) Decoder. [Citation Graph (, )][DBLP]
A New Early Termination Scheme of Iterative Turbo Decoding Using Decoding Threshold. [Citation Graph (, )][DBLP]
Pipelined ALU for Signal Processing to Implement Interval Arithmetic. [Citation Graph (, )][DBLP]
H.264 Video Encoder Implementation on a Low-power DSP with Low and Stable Computational Complexity. [Citation Graph (, )][DBLP]
H.264 Video Decoder Design: Beyond RTL Design Implementation. [Citation Graph (, )][DBLP]
An Iterative Method for Frame-Level Adaptive Wiener Interpolation Filters in Video Coding. [Citation Graph (, )][DBLP]
A Theoretical Model and Study of Weighted MCTF Residual Energy. [Citation Graph (, )][DBLP]
VSIP : Video Specific Instruction Set Processor for H.264/AVC. [Citation Graph (, )][DBLP]
Motion Compensated Frame Rate Conversion Using a Specialized Instruction Set Processor. [Citation Graph (, )][DBLP]
High-Speed Pipelined EGG Processor on FPGA. [Citation Graph (, )][DBLP]
A Reconfigurable Applcation Specific Instruction Set Processor for Viterbi and Log-MAP Decoding. [Citation Graph (, )][DBLP]
Lossless Compression Using Two-Level and Multilevel Boolean Minimization. [Citation Graph (, )][DBLP]
Limiting Flexibility in Multiplication over GF(2m): A Design Methodology. [Citation Graph (, )][DBLP]
0.35 m 22W Multiphase Programmable Clock Generator for Circular Memory SC FIR Filter For Wireless Sensor Applications. [Citation Graph (, )][DBLP]
Semi-Blind Channel Estimation for OFDM using Least Squares. [Citation Graph (, )][DBLP]
A Robust Band-Tracking Packet Detector (BT-PD) in OFDM-Based Ultra-Wideband Systems. [Citation Graph (, )][DBLP]
A Low Cost Packet Detector in OFDM-Based Ultra-Wideband Systems. [Citation Graph (, )][DBLP]
EM-based Channel Estimation for Space Time Block Coded MIMO OFDM Systems. [Citation Graph (, )][DBLP]
FPGA Implementation of Pipelined Architecture for Optical Imaging Distortion Correction. [Citation Graph (, )][DBLP]
A Low-Power Folded Programmable FIR Architecture. [Citation Graph (, )][DBLP]
An Examination of the Effect of Feature Size Scaling on Effective Power Consumption in Analog to Digital Converters. [Citation Graph (, )][DBLP]
Low-Power Saturated Arithmetic and its Application in VLSI Architectures for OFDM Modems. [Citation Graph (, )][DBLP]
Low Power Trellis Decoder with Overscaled Supply Voltage. [Citation Graph (, )][DBLP]
Simplified Criteria for Early Iterative Decoding Termination. [Citation Graph (, )][DBLP]
Fixed-to-Variable Length Source Coding Using Turbo Codes. [Citation Graph (, )][DBLP]
Partly Parallel Overlapped Sum-Product Decoder Architectures for Quasi-Cyclic LDPC Codes. [Citation Graph (, )][DBLP]
On the Effects of Colored Noise on the Performance of LDPC Codes. [Citation Graph (, )][DBLP]
An Optimal Adaptive M-PSK Carrier Phase Detector Suitable for Fixed-Point Hardware Implementation within FPGAs and ASICs. [Citation Graph (, )][DBLP]
Automated derivation of NoC Communication Specifications from Application Constraints. [Citation Graph (, )][DBLP]
Design Space Exploration of DSP Applications Based on Behavioral Description Models. [Citation Graph (, )][DBLP]
Evaluating SoC Network Performance in MPEG-4 Encoder. [Citation Graph (, )][DBLP]
Transparent Embedded Compression in Systems-on-Chip. [Citation Graph (, )][DBLP]
Low Complexity Implementations of Sum-Product Algorithm for Decoding Low-Density Parity-Check Codes. [Citation Graph (, )][DBLP]
Spatial Optical Distortion Correction in an FPGA. [Citation Graph (, )][DBLP]
Automated Architectural Exploration for Signal Processing Algorithms. [Citation Graph (, )][DBLP]
Bit-Width Optimizations for High-Level Synthesis of Digital Signal Processing Systems. [Citation Graph (, )][DBLP]
Automatic Generation of Programmable Parallel CRC & Scrambler Designs. [Citation Graph (, )][DBLP]
Instruction Transfer And Storage Exploration for Low Energy VLIWs. [Citation Graph (, )][DBLP]
Fault Tolerance of Quantized Unitary Precoders. [Citation Graph (, )][DBLP]
Low-Power High-Throughput BCH Error Correction VLSI Design for Multi-Level Cell NAND Flash Memories. [Citation Graph (, )][DBLP]
A Shortened Impulse Response Filter (SIRF) Scheme for Cost-Effective Echo Canceller Design of 10GBase-T Ethernet System. [Citation Graph (, )][DBLP]
On the Convergence of the Frequency-Domain LMS Adaptive Filter using LMS-DFT. [Citation Graph (, )][DBLP]
FPGA Implementation of Adaptive Filters based on GSFAP using Log Arithmetic. [Citation Graph (, )][DBLP]
SystemC Model of an Interoperative GPS/Galileo Code Correlator Channel. [Citation Graph (, )][DBLP]
Desing and Optimization of a Programmable Instruction Decoder for DSP Architecture. [Citation Graph (, )][DBLP]
Carry Prediction and Selection for Truncated Multiplication. [Citation Graph (, )][DBLP]
Carry Estimation for Two's Complement Fixed-Width Multipliers. [Citation Graph (, )][DBLP]
Subword-Parallel VLIW Architecture Exploration for Multimode Software Defined Radio. [Citation Graph (, )][DBLP]
On The Identification of Snow Movements on Roads. [Citation Graph (, )][DBLP]
Software-Controlled Scratchpad Mapping Strategies for Wavelet-Based Applications. [Citation Graph (, )][DBLP]
An Area Efficient Real-time CAVLC IP-Block towards the H.264/AVC Encoder. [Citation Graph (, )][DBLP]
A Method for Object Tracking using Shape Matching. [Citation Graph (, )][DBLP]
Efficient Memory Reuse and Sub-Pixel Interpolation Algorithms for ME/MC of H.264/AVC. [Citation Graph (, )][DBLP]
An Efficient Data Reuse Motion Estimation Engine. [Citation Graph (, )][DBLP]
A VLSI 8×8 MIMO Near-ML Decoder Engine. [Citation Graph (, )][DBLP]
An Energy-Efficient Reconfigurable Baseband Processor for Flexible Radios. [Citation Graph (, )][DBLP]
SmartMIMO: Energy-Aware Adaptive MIMO-OFDM Radio Link Control for Wireless Local Area Networks. [Citation Graph (, )][DBLP]
Architecture-Aware LDPC Code Design for Software Defined Radio. [Citation Graph (, )][DBLP]
Adaptive Tap Management in Multi-Gigabit Echo & Next Cancellers. [Citation Graph (, )][DBLP]
Analog-Counter-Based Conscience Mechanism in Kohonen's Neural Network Implemented in CMOS 0.18 m Technology. [Citation Graph (, )][DBLP]
On-Line MSR-CORDIC VLSI Architecture with Applications to Cost-Efficient Rotation-Based Adaptive Filtering Systems. [Citation Graph (, )][DBLP]
Design and Implementation of JPEG 2000 Codec with Bit-Plane Scalable Architecture. [Citation Graph (, )][DBLP]
A Low-Complexity PTS-based PAPR Reduction Technique for OFDM Signals without Transmission of Side Information. [Citation Graph (, )][DBLP]
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