Conferences in DBLP

(3dic)
2009 (conf/3dic/2009)

1. 
   Junction-level thermal extraction and simulation of 3DICs. [Citation Graph (, )][DBLP]
   
   
2. 
   Fabrication and packaging of microbump interconnections for 3D TSV. [Citation Graph (, )][DBLP]
   
   
3. 
   High speed I/O and thermal effect characterization of 3D stacked ICs. [Citation Graph (, )][DBLP]
   
   
4. 
   Effect of resistance of TSV's on performance of boost converter for low power 3D SSD with NAND flash memories. [Citation Graph (, )][DBLP]
   
   
5. 
   Development of Functionally innovative 3D-Integrated Circuit (Dream Chip) technology / High-Density 3D-Integration Technology for Multifunctional Devices. [Citation Graph (, )][DBLP]
   
   
6. 
   Impact of thermal through silicon via (TTSV) on the temperature profile of multi-layer 3-D device stack. [Citation Graph (, )][DBLP]
   
   
7. 
   A review of wafer bonding materials and characterizations to enable wafer thinning, backside processing, and laser dicing. [Citation Graph (, )][DBLP]
   
   
8. 
   Chip-to-chip communication based on capacitive coupling. [Citation Graph (, )][DBLP]
   
   
9. 
   3-D thin chip integration technology - from technology development to application. [Citation Graph (, )][DBLP]
   
   
10. 
    Heterogeneous integration technology for MEMS-LSI multi-chip module. [Citation Graph (, )][DBLP]
    
    
11. 
    A capacitive coupling interface with high sensitivity for wireless wafer testing. [Citation Graph (, )][DBLP]
    
    
12. 
    Validation of the porous-medium approach to model interlayer-cooled 3D-chip stacks. [Citation Graph (, )][DBLP]
    
    
13. 
    Robust verification of 3D-ICs: Pros, cons and recommendations. [Citation Graph (, )][DBLP]
    
    
14. 
    Wet-process deposition of TSV liner and metal films. [Citation Graph (, )][DBLP]
    
    
15. 
    Evolution of bond technology to hybridized process flows. [Citation Graph (, )][DBLP]
    
    
16. 
    3D optical networks-on-chip (NoC) for multiprocessor systems-on-chip (MPSoC). [Citation Graph (, )][DBLP]
    
    
17. 
    A parallel ADC for high-speed CMOS image processing system with 3D structure. [Citation Graph (, )][DBLP]
    
    
18. 
    Through-Silicon Via (TSV)-induced noise characterization and noise mitigation using coaxial TSVs. [Citation Graph (, )][DBLP]
    
    
19. 
    Electrical modeling of Through Silicon and Package Vias. [Citation Graph (, )][DBLP]
    
    
20. 
    Thermal analysis for a SiGe HBT 40 watt 32 GHz clock 3D memory processor chip stack using diamond heat spreader layers. [Citation Graph (, )][DBLP]
    
    
21. 
    Technology impact analysis for 3D TCAM. [Citation Graph (, )][DBLP]
    
    
22. 
    Micro-Raman spectroscopy analysis and capacitance - time (C-t) measurement of thinned silicon substrates for 3D integration. [Citation Graph (, )][DBLP]
    
    
23. 
    10 µm fine pitch Cu/Sn micro-bumps for 3-D super-chip stack. [Citation Graph (, )][DBLP]
    
    
24. 
    Predictive High Frequency effects of substrate coupling in 3D integrated circuits stacking. [Citation Graph (, )][DBLP]
    
    
25. 
    A route towards production-worthy 5 µm × 25 µm and 1 µm × 20 µm non-Bosch through-silicon-via (TSV) etch, TSV metrology, and TSV integration. [Citation Graph (, )][DBLP]
    
    
26. 
    Architectural evaluation of 3D stacked RRAM caches. [Citation Graph (, )][DBLP]
    
    
27. 
    TSV metrology and inspection challenges. [Citation Graph (, )][DBLP]
    
    
28. 
    Investigation and comparison of thermal distribution in synchronous and asynchronous 3D ICs. [Citation Graph (, )][DBLP]
    
    
29. 
    Reliability aspects of 3D-oriented heterogeneous device design related to stress sensitivity of MOS transistors. [Citation Graph (, )][DBLP]
    
    
30. 
    Die stacking using 3D-wafer level packaging copper/polymer through-si via technology and Cu/Sn interconnect bumping. [Citation Graph (, )][DBLP]
    
    
31. 
    3D integration technology for 3D stacked retinal chip. [Citation Graph (, )][DBLP]
    
    
32. 
    System-level comparison of power delivery design for 2D and 3D ICs. [Citation Graph (, )][DBLP]
    
    
33. 
    First integration of Cu TSV using die-to-wafer direct bonding and planarization. [Citation Graph (, )][DBLP]
    
    
34. 
    SrTiO3 thin film decoupling capacitors on Si interposers for 3D system integration. [Citation Graph (, )][DBLP]
    
    
35. 
    An innovative die to wafer 3D integration scheme: Die to wafer oxide or copper direct bonding with planarised oxide inter-die filling. [Citation Graph (, )][DBLP]
    
    
36. 
    3D Stacked IC demonstrator using Hybrid Collective Die-to-Wafer bonding with copper Through Silicon Vias (TSV). [Citation Graph (, )][DBLP]
    
    
37. 
    Delay analysis and design exploration for 3D SRAM. [Citation Graph (, )][DBLP]
    
    
38. 
    Impact of parameter accuracy on 3D design. [Citation Graph (, )][DBLP]
    
    
39. 
    Material improvement for ultrathin-wafer handling in TSV creation and PECVD process. [Citation Graph (, )][DBLP]
    
    
40. 
    IC-package co-design and analysis for 3D-IC designs. [Citation Graph (, )][DBLP]
    
    
41. 
    Thin wafer handling - Study of temporary wafer bonding materials and processes. [Citation Graph (, )][DBLP]
    
    
42. 
    3D on-chip memory for the vector architecture. [Citation Graph (, )][DBLP]
    
    
43. 
    Design tools for the 3D roadmap. [Citation Graph (, )][DBLP]
    
    
44. 
    Electrical-thermal co-analysis for power delivery networks in 3D system integration. [Citation Graph (, )][DBLP]
    
    
45. 
    Arithmetic unit design using 180nm TSV-based 3D stacking technology. [Citation Graph (, )][DBLP]
    
    
46. 
    Development of wafer thinning and dicing technology for thin wafer. [Citation Graph (, )][DBLP]
    
    
47. 
    A routerless system level interconnection network for 3D integrated systems. [Citation Graph (, )][DBLP]
    
    
48. 
    3D TSV processes and its assembly/packaging technology. [Citation Graph (, )][DBLP]
    
    
49. 
    Evaluation of fine grain 3-D integrated arithmetic units. [Citation Graph (, )][DBLP]
    
    
50. 
    3D integration technology for set-top box application. [Citation Graph (, )][DBLP]
    
    
51. 
    Physical mapping and performance study of a multi-clock 3-Dimensional Network-on-Chip mesh. [Citation Graph (, )][DBLP]
    
    
52. 
    Development of feed-forward design system for rapid SiP design. [Citation Graph (, )][DBLP]
    
    
53. 
    Thermal resistance measurements of interconnections for a three-dimensional (3D) chip stack. [Citation Graph (, )][DBLP]
    
    
54. 
    A tileable switch module architecture for homogeneous 3D FPGAs. [Citation Graph (, )][DBLP]
    
    
55. 
    3-D memory organization and performance analysis for multi-processor network-on-chip architecture. [Citation Graph (, )][DBLP]
    
    
56. 
    Development of a new self-assembled die bonder to three-dimensionally stack known good dies in batch. [Citation Graph (, )][DBLP]
    
    
57. 
    Comparative analysis of two 3D integration implementations of a SAR processor. [Citation Graph (, )][DBLP]
    
    
58. 
    Modeling and evaluation for electrical characteristics of through-strata-vias (TSVS) in three-dimensional integration. [Citation Graph (, )][DBLP]
    
    
59. 
    Evaluation of energy-recovering interconnects for low-power 3D stacked ICs. [Citation Graph (, )][DBLP]
    
    
60. 
    Thermotropic liquid crystalline polyimides toward high heat conducting materials for 3D chip stack. [Citation Graph (, )][DBLP]
    
    
61. 
    3D interconnects for dense die stack packages. [Citation Graph (, )][DBLP]
    
    
62. 
    Advanced wafer bonding solutions for TSV integration with thin wafers. [Citation Graph (, )][DBLP]
    
    
63. 
    Ultralow impedance evaluation system of wideband frequency for power distribution network of decoupling capacitor embedded substrates. [Citation Graph (, )][DBLP]
    
    
64. 
    Impacts of though-DRAM vias in 3D processor-DRAM integrated systems. [Citation Graph (, )][DBLP]
    
    
65. 
    Modelling of Through Silicon Via RF performance and impact on signal transmission in 3D integrated circuits. [Citation Graph (, )][DBLP]
    
    
66. 
    Compact modelling of Through-Silicon Vias (TSVs) in three-dimensional (3-D) integrated circuits. [Citation Graph (, )][DBLP]
    
    
67. 
    Low Cost of Ownership scalable copper Direct Bond Interconnect 3D IC technology for three dimensional integrated circuit applications. [Citation Graph (, )][DBLP]
    
    
68. 
    Miniature wireless activity monitor using 3D system integration. [Citation Graph (, )][DBLP]
    
    
69. 
    Achieving low temperature Cu to Cu diffusion bonding with self assembly monolayer (SAM) passivation. [Citation Graph (, )][DBLP]
    
    
70. 
    Automated Pathfinding tool chain for 3D-stacked integrated circuits: Practical case study. [Citation Graph (, )][DBLP]
    
    
71. 
    Aluminum-Germanium eutectic bonding for 3D integration. [Citation Graph (, )][DBLP]
    
    
72. 
    Impact of 3D design choices on manufacturing cost. [Citation Graph (, )][DBLP]
    
    
73. 
    3D integrated circuits for lab-on-chip applications. [Citation Graph (, )][DBLP]
    
    
74. 
    Influence of 3D integration on 2D interconnections and 2D self inductors HF properties. [Citation Graph (, )][DBLP]
    
    
75. 
    Etch, dielectrics and metal barrier-seed for low temperature through-silicon via processing. [Citation Graph (, )][DBLP]
    
    
76. 
    Developments of novel vertically integrated pixel sensors in the high energy physics community. [Citation Graph (, )][DBLP]
    
    
77. 
    The benefits of 3D networks-on-chip as shown with LDPC decoding. [Citation Graph (, )][DBLP]
    
    
78. 
    Wafer-scale 3D integration of InGaAs image sensors with Si readout circuits. [Citation Graph (, )][DBLP]
    
    
79. 
    Through Silicon Via(TSV) defect/pinhole self test circuit for 3D-IC. [Citation Graph (, )][DBLP]
    
    
80. 
    Wafer Thickness Sensor (WTS) for etch depth measurement of TSV. [Citation Graph (, )][DBLP]
    
    
81. 
    Advanced 3D chip stack process for thin dies with fine pitch bumps using pre-applied inter chip fill. [Citation Graph (, )][DBLP]