Conferences in DBLP
Samar Saha , Bhaskar Gadepally Technology CAD: Technology Modeling, Device Design and Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Susmita Sur-Kolay , Parthasarathi Dasgupta , Bhargab B. Bhattacharya , Sujit T. Zachariah Physical Design Trends and Layout-Based Fault Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Rajarshi Mukherjee , Mukul R. Prasad , Masahiro Fujita High Level Design Validation: Current Practices and Future Directions. [Citation Graph (0, 0)][DBLP ] Conf ] Krithi Ramamritham , Kavi Arya , Gerhard Fohler System Software for Embedded Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Siva Narendra , Vasantha Erraguntla , James Tschanz , Nitin Borkar Design Challenges in Sub-100nm High Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel , Jordi Cortadella , Alex Kondratyev Bridging the Gap between Asynchronous Design and Designers. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Rajski , Nilanjan Mukherjee , Jerzy Tyszer , Thomas Rinderknecht Embedded Test for Low Cost Manufacturing. [Citation Graph (0, 0)][DBLP ] Conf ] Gérard Berry Synchronous Methodology for Designing Hardware, Software and Mixed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] P. Jespers High Speed Integrated A to D Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroshi Iwai CMOS Scaling for sub-90 nm to sub-10 nm. [Citation Graph (0, 0)][DBLP ] Conf ] Jaime Ramírez-Angulo , Ramón González Carvajal , Antonio J. López-Martín Techniques for very low-voltage operation of continuous-time analog CMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Srinjoy Mitra , A. N. Chandorkar Design of Amplifier with Rail-to-Rail CMR with 1V Power Supply. [Citation Graph (0, 0)][DBLP ] Conf ] S. V. Gopalaiah , A. P. Shivaprasad , Sukanta K. Panigrahi Design of Low Voltage Low Power CMOS OP-AMPS with Rail-to-Rail Input/Output Swing. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Raychowdhury , Saibal Mukhopadhyay , Kaushik Roy Modeling and Estimation of Leakage in Sub-90nm Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Maitrali Marik , Ajit Pal Energy-aware Logic Synthesis and Technology Mapping for MUX-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] D. Satyanarayana , Santanu Chattopadhyay , Jakki Sasidhar Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Debasis Samanta , Ajit Pal Synthesis of Low Power High Performance Dual-VT PTL Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Masahiro Fujita Formal Verification of C Language Based VLSI Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Ansuman Banerjee , Pallab Dasgupta , P. P. Chakrabarti Formal Verification of Modules under Real Time Environment Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Prasenjit Basu , Pallab Dasgupta , P. P. Chakrabarti , Chunduri Rama Mohan Property Refinement Techniques for Enhancing Coverage of Formal Property Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Narayanan Krishnamurthy , Jayanta Bhadra , Magdy S. Abadir , Jacob A. Abraham Towards The Complete Elimination of Gate/Switch Level Simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Sujay Phadke , Rhishikesh Limaye , Siddharth Verma , Kavitha Subramanian On Design and Implementation of an Embedded Automatic Speech Recognition System. [Citation Graph (0, 0)][DBLP ] Conf ] Theo Theocharides , Greg M. Link , Narayanan Vijaykrishnan , Mary Jane Irwin , Wayne Wolf Embedded Hardware Face Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Jaijeet S. Roychowdhury Algorithmic Macromodelling Methods for Mixed-Signal Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hao San , Haruo Kobayashi , Shinya Kawakami , Nobuyuki Kuroiwa An Element Rotation Algorithm for Multi-bit DAC Nonlinearities in Complex Bandpass \Delta\SigmaAD Modulators. [Citation Graph (0, 0)][DBLP ] Conf ] Anup Savla , Jennifer Leonard , Arun Ravindran Error Correction In Pipelined ADCS Using Arbitrary Radix Calibration. [Citation Graph (0, 0)][DBLP ] Conf ] Rasoul Dehghani A 2.5GHz CMOS Fully-Integrated \Delta\Sigma-Controlled Fractional-N Frequency Synthesizer. [Citation Graph (0, 0)][DBLP ] Conf ] Nitin Bansal , Amit Katyal A Switch-Cap Regulator for SoC Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald W. Mehler , Dian Zhou Automated Architectural Optimization of Digital FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Rui Min , Zhiyong Xu , Yiming Hu , Wen-Ben Jone Partial Tag Comparison: A New Technology for Power-Efficient Set-Associative Cache Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay D'Silva , S. Ramesh , Arcot Sowmya Bridge Over Troubled Wrappers: Automated Interface Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Murugavel , N. Ranganathan Gate Sizing and Buffer Insertion using Economic Models for Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Seok-Soo Yoon , Seok-Ryong Yoon , Seon Wook Kim , Chulwoo Kim Charge-Sharing-Problem Reduced Split-Path Domino Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Krishnan , José Pineda de Gyvez Low Energy Switch Block For FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Sergey Romanovsky , Arun Achyuthan , Sreedhar Natarajan , Wing Leung Leakage Reduction techniques in a 0.13um SRAM Cell. [Citation Graph (0, 0)][DBLP ] Conf ] Ge Yang , Zhongda Wang , Sung-Mo Kang Leakage-Proof Domino Circuit Design for Deep Sub-100nm Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Narender Hanchate , Nagarajan Ranganathan A New Technique for Leakage Reduction in CMOS Circuits using Self-Controlled Stacked Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul M. Rao , Jeffrey L. Burns , Richard B. Brown Analysis and Optimization of Enhanced MTCMOS Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Kaviraj Chopra , Sarma B. K. Vrudhula , Sarvesh Bhardwaj Efficient Algorithms for Identifying the Minimum Leakage States in CMOS Combinational Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Yodaiken New frontiers for embedded computing. [Citation Graph (0, 0)][DBLP ] Conf ] Krishnan Srinivasan , Karam S. Chatha An ILP Formulation for System Level Throughput and Power Optimization in Multiprocessor SoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yunsi Fei , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Energy-Optimizing Source Code Transformations for OS-driven Embedded Software. [Citation Graph (0, 0)][DBLP ] Conf ] Weidong Wang , Anand Raghunathan , Niraj K. Jha Profiling Driven Computation Reuse: An Embedded Software Synthesis Technique for Energy and Performance Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Cor Claeys Technological Challenges of Advanced CMOS Processing and Their Impact on Design Aspects. [Citation Graph (0, 0)][DBLP ] Conf ] H. C. Srinivasaiah , Navakanta Bhat Response Surface Modeling of 100nm CMOS Process Technology using Design of Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Purushothaman Srinivasan , B. Vootukuru , Durga Misra Screening of Hot Electron Effect During Plasma Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Satnam Singh Designing Reconfigurable Systems in Lava. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Sekar , Kanishka Lahiri , Sujit Dey Configurable Platforms With Dynamic Platform Management: An Efficient Alternative to Application-Specific System-on-Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Kausik Datta , P. P. Das Assertion Based Verification Using HDVL. [Citation Graph (0, 0)][DBLP ] Conf ] Tun Li , Yang Guo , Sikun Li Design and Implementation of a Parallel Verilog Simulator: PVSim. [Citation Graph (0, 0)][DBLP ] Conf ] Raghukiran Sreeramaneni , Sarma B. K. Vrudhula Energy Profiler for Hardware/Software Co-Design. [Citation Graph (0, 0)][DBLP ] Conf ] Tezaswi Raja , Vishwani D. Agrawal , Michael L. Bushnell A Tuturial on the Emerging Nanotechnology Devices. [Citation Graph (0, 0)][DBLP ] Conf ] David D. Wentzloff , Benton H. Calhoun , Rex Min , Alice Wang , Nathan Ickes , Anantha Chandrakasan Design Considerations for Next Generation Wireless Power-Aware Microsensor Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Witowsky A Vision for the Broadband Network. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Monticelli A System Approach to Energy Management. [Citation Graph (0, 0)][DBLP ] Conf ] Phil Moorby Design for Verification with SystemVerilog. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjive Agarwala , Paul Wiley , Arjun Rajagopal , Anthony M. Hill , Raguram Damodaran , Lewis Nardini , Tim Anderson , Steven Mullinnix , Jose Flores , Heping Yue , Abhijeet Chachad , John Apostol , Kyle Castille , Usha Narasimha , Tod Wolf , N. S. Nagaraj , Manjeri Krishnan , Luong Nguyen , Todd Kroeger , Mike Gill , Peter Groves , Bill Webster , Joel Graber , Christine Karlovich A 800 MHz System-on-Chip for Wireless Infrastructure Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Long , Robert J. Weber A Low Voltage, Low Noise CMOS RF Receiver Front-End. [Citation Graph (0, 0)][DBLP ] Conf ] V. Veeresh Babu , Sumantra Seth , A. N. Chandorkar Design of RF Tuner for Cable Modem Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Amlan Ghosh , Bevin G. Perumana , Ashudeb Dutta , Padmanava Sen , Yogesh Kumar , Vipul Garg , T. K. Bhattacharyya , Nirmal B. Chakrabarti Design and Implementation of 935 MHz FM Transceiver for Radio Telemetry and 2.45 GHz Direct AQPSK Transmitter in CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Padmanava Sen , Vipul Garg , Ramesh Garg , Nirmal B. Chakrabarti Design of Power Amplifiers at 2.4 GHz/900 MHz and Implementation of On-chip Linearization Technique in 0.18/0.25 ?I`m CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] T. Hui Teo , Ee-Sze Khoo , Dasgupta Uday , Chin-Boon Tear Design, Analysis, and Implementation of Analog Complex Filter for Low-IF Wireless LAN Application. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Tom Bonifield , Abha Singh , Roger Griesmer , Poras T. Balsara Interconnect Modeling for Copper/Low-k Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng Wire Swizzling to Reduce Delay Uncertainty Due to Capacitive Coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Marong Phadoongsidhi , Kewal K. Saluja Static Timing Analysis of Irreversible Crosstalk Noise Pulse Faults. [Citation Graph (0, 0)][DBLP ] Conf ] P. Subrahmanya , R. Manimegalai , V. Kamakoti , Madhu Mutyam A Bus Encoding Technique for Power and Cross-talk Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Suvodeep Gupta , Srinivas Katkoori Intra-Bus Crosstalk Estimation Using Word-Level Statistics. [Citation Graph (0, 0)][DBLP ] Conf ] Vani Prasad , Madhav P. Desai On Buffering Schemes for Long Multi-Layer Nets. [Citation Graph (0, 0)][DBLP ] Conf ] Salvador Mir , Libor Rufer , Bernard Courtois On-chip testing of embedded transducers. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Srikanth Venkataraman , Sudhakar M. Reddy , Enamul Amyeen Defect Diagnosis Based on Pattern-Dependent Stuck-At Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Manan Syal , Michael S. Hsiao Untestable Fault Identification using Recurrence Relations and Impossible Value Assignments. [Citation Graph (0, 0)][DBLP ] Conf ] Hafizur Rahaman , Debesh K. Das , Bhargab B. Bhattacharya Easily Testable Realization of GRM and ESOP Networks for Detecting Stuck-at and Bridging Faults. [Citation Graph (0, 0)][DBLP ] Conf ] Josh Yang , Baosheng Wang , André Ivanov Open Defects Detection within 6T SRAM Cells using a No Write Recovery Test Mode. [Citation Graph (0, 0)][DBLP ] Conf ] Pan Zhongliang Neural Network Model for Testing Stuck-at and Delay Faults in Digital Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Mahesh Mehendale Challenges in the Design of Embedded Real-time DSP SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] C. P. Ravikumar Multiprocessor Architectures for Embedded System-on-chip Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ramalingam Sridhar System-on-Chip (SoC): Clocking and Synchronization Issues. [Citation Graph (0, 0)][DBLP ] Conf ] P. R. Suresh , P. K. Sundararajan , Anshuli Goel , H. Udayakumar , C. Srinivasan , Vasudev Sinari , Raghavendrakumar Ravinutala Package-silicon co-design - Experiment with an SOC design. [Citation Graph (0, 0)][DBLP ] Conf ] Qadeer Ahmad Khan , Sanjay Kumar Wadhwa , Kulbhushan Misri A tunable gm-C filter with low variation across Process, Voltage and Temperature. [Citation Graph (0, 0)][DBLP ] Conf ] K. Narasimhulu , Siva Narendra , V. Ramgopal Rao The Influence of Process Variations on the Halo MOSFETs and its Implications on the Analog Circuit performance. [Citation Graph (0, 0)][DBLP ] Conf ] S. S. Prasad , Pradip Mandal A CMOS Beta Multiplier Voltage Reference with Improved Temperature Performance and Silicon Tunability. [Citation Graph (0, 0)][DBLP ] Conf ] Joycee Mekie , Supratik Chakraborty , Dinesh K. Sharma Evaluation of pausible clocking for interfacing high speed IP cores in GALS Framework. [Citation Graph (0, 0)][DBLP ] Conf ] G. Hazari , Madhav P. Desai , A. Gupta , S. Chakraborty A Novel Technique Towards Eliminating the Global Clock in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Aditya Mittal , Madhav P. Desai A Distributed and Pipelined Controller for a Modular and Scalable Hardware Emulator. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Bieger , Sorin A. Huss , Michael Jung , Stephan Klaus , Thomas Steininger Rapid Prototyping for Configurable System-on-a-Chip Platforms: A Simulation Based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Mukul R. Prasad , Michael S. Hsiao , Jawahar Jain Can SAT be used to Improve Sequential ATPG Methods? [Citation Graph (0, 0)][DBLP ] Conf ] Vivekananda M. Vedula , Whitney J. Townsend , Jacob A. Abraham Program Slicing for ATPG-Based Property Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Aman Kokrady , C. P. Ravikumar Fast, Layout-Aware Validation of Test-Vectors for Nanometer-Related Timing Failures. [Citation Graph (0, 0)][DBLP ] Conf ] Srivaths Ravi , Anand Raghunathan , Srimat T. Chakradhar Tamper Resistance Mechanisms for Secure, Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] R. Dehghani , Seyed Mojtaba Atarodi , B. Bornoosh , Ali Afzali-Kusha A Reduced Complexity 3rd Order Digital Delta-Sigma Modulator for Fractional-N Frequency Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] S. Nagar , Baquer Mazhari A New Approach To Topology Selection For Cell-Level Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Gagandeep S. Sandha , Pawan K. Singh , C. Pradeep Kumar , D. Nagchoudhuri Quantitative Model for Thermal Behaviour of an Analog Integrated Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Ghanshyam Nayak , P. R. Mukund Chip Package Co-Design of a Heterogeneously Integrated 2.45GHz CMOS VCO using Embedded Passives in a Silicon Package. [Citation Graph (0, 0)][DBLP ] Conf ] M. Benmansour , P. R. Mukund A Tuned Wideband LNA in 0.25?I`m IBM Process For RF Communication Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tejasvi Das , P. R. Mukund A Low Noise Current-mode Readout circuit for CMOS Image Sensing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] F. Farbiz , M. Farazian , M. Emadi , K. Sadeghi Sizing Consideration for Leakage Control Transistor. [Citation Graph (0, 0)][DBLP ] Conf ] S. Jairam , C. Venkatesh , Navakanta Bhat , Shyam Singh , Rudra Pratap A Quasi Static Model for a Simply Supported Beam in a Circuit Simulation Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Shrutin Ulman Analytical Expressions For Static Characteristics of Submicron CMOS Inverters. [Citation Graph (0, 0)][DBLP ] Conf ] Venkat Rao , Gaurav Singhal , Anshul Kumar Real Time Dynamic Voltage Scaling For Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] M. DeRenzo , Mary Jane Irwin , Narayanan Vijaykrishnan Designing Leakage Aware Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Dainius Ciuplys , Per Larsson-Edefors On Maximum Current Estimation in CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Anurag Chaudhry , M. Jagadesh Kumar Exploring the Novel Characteristics of Fully Depleted Dual-Material Gate (DMG) SOI MOSFET using Two-Dimensional Numerical Simulation Studies. [Citation Graph (0, 0)][DBLP ] Conf ] Ashis Kumar Mal , Anindya Sundar Dhar Analog VLSI Architecture for Discrete Cosine Transform using Dynamic Switched Capacitors. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Murugavel , N. Ranganathan Game Theoretic Modeling of Voltage and Frequency Scaling during Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] N. Sudha An ASIC Implementation of Kohonen's Map Based Color Image Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Jen Yen , Wen-Yaw Chung , Mely Chen Chi A Compact Low-Power Buffer Amplifier with Dynamic Bias Control Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Madhu Mutyam Preventing Crosstalk Delay using Fibonacci Representation. [Citation Graph (0, 0)][DBLP ] Conf ] N. Sudha An Area-Efficient Pipelined Array Architecture for Euclidean Distance Transformation and Its FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Mikael Millberg , Erland Nilsson , Rikard Thid , Shashi Kumar , Axel Jantsch The Nostrum Backbone - a Communication Protocol Stack for Networks on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Manvendra Singh , B. S. Chauhan , N. K. Sharma VLSI Architecture of Centroid Tracking Algorithms for Video Tracker. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Mandal A Narrow Pulse- Suppressing Filter For Input Buffer. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin Shrivastava , Dhanoop Varghese , Vikas Narang , N. V. Arvind Improved Approach for Noise Propagation to Identify Functional Noise Violations. [Citation Graph (0, 0)][DBLP ] Conf ] Sreeram Chandrasekar , Sachin Shrivastava , Ajoy Mandal , Sornavalli Ramanathan An Efficient Approach to Crosstalk Noise Analysis at Multiple Operating Modes. [Citation Graph (0, 0)][DBLP ] Conf ] Stelian Alupoaei , Srinivas Katkoori Energy Model Based Macrocell Placement for Wirelength Minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Jeremy Chan , Sri Parameswaran NoCGEN: A Template Based Reuse Methodology for Networks on Chip Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai Net Buffering in the Presence of Multiple Timing Views. [Citation Graph (0, 0)][DBLP ] Conf ] N. V. Arvind , K. A. Rajagopal , H. S. Ajith , Das Suparna Path Based Approach for Crosstalk Delay Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Varun Jindal , Alpana Agarwal Carry Circuitry for LUT-Based FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Fuminori Kobayashi An Optically Differential Reconfigurable Gate Array with a partial reconfiguration optical system and its power consumption estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On Interconnecting Circuits with Multiple Scan Chains for Improved Test Data Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , Nagarajan Ranganathan , Sunil K. Chappidi ILP Models for Energy and Transient Power Minimization During Behavioral Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Syed Saif Abrar Cycle-Accurate Energy Model and Source-Independent Characterization Methodology for Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeshwar S. Sable , Ravindra P. Saraf , Rubin A. Parekhji , Arun N. Chandorkar Built-in Self-test Technique for Selective Detection of Neighbourhood Pattern Sensitive Faults in Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Hafiz Md. Hasan Babu , Md. Rafiqul Islam , Syed Mostahed Ali Chowdhury , Ahsan Raja Chowdhury Synthesis of Full-Adder Circuit Using Reversible Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Sourabh Saluja , Anshul Kumar Performance Analysis of Inter Cluster Communication Methods in VLIW Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Nilesh Modi , Jordi Cortadella Boolean Decomposition Using Two-literal Divisors. [Citation Graph (0, 0)][DBLP ] Conf ] Nirav Patel , M. Srihari , Pooja Maheswari , G. N. Nandakumar An Efficient Method to Generate Test Vectors for Combinational Cell Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Saini , Pramod Tanwar , A. S. Mandal , S. C. Bose , Raj Singh , Chandra Shekhar Design of an Application Specific Instruction Set Processor for Parametric Speech Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Gurashish Singh Brar , Susmit Biswas , Sudipta Kundu , Arijit Mukhopadhyay , Pratik Worah , Anupam Basu OaSis: An Application Specific Operating System for an Embedded Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Basant Kumar Dwivedi , Anshul Kumar , M. Balakrishnan Synthesis of Application Specific Multiprocessor Architectures for Process Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Rajat Arora , Michael S. Hsiao Enhancing SAT-based Bounded Model Checking using Sequential Logic Implications. [Citation Graph (0, 0)][DBLP ] Conf ] Subrangshu Das , Subash G. Chandar , Ashutosh Tiwari Reset Careabouts in a SoC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Raman Srinivas Building Giga-Transistor [Enterprise] Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] M. K. Radhakrishnan Device Reliability and Failure Mechanisms Related to Gate Dielectrics and Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Harald Gossner ESD protection for the deep sub micron regime - a challenge for design methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Tushar S. Shelar , G. S. Visweswaran Inclusion of Thermal Effects in the Simulation of Bipolar Circuits using Circuit Level Behavioral Modeling. [Citation Graph (0, 0)][DBLP ] Conf ] M. Jagadesh Kumar , Vinod Parihar A New Surface Accumulation Layer Transistor(SALTran) Concept for Current Gain Enhancement in Bipolar Transistors. [Citation Graph (0, 0)][DBLP ] Conf ] Rajiv V. Joshi , K. Kroell , Ching-Te Chuang A Novel Technique For Steady State Analysis For VLSI Circuits In Partially Depleted SOI. [Citation Graph (0, 0)][DBLP ] Conf ] Sachin S. Sapatnekar High-Performance Power Grids For Nanometer Technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel , Wayne Wolf , Srimat T. Chakradhar On-chip networks: A scalable, communication-centric embedded system design paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Gary William Grewal , Thomas Charles Wilson , Ming Xu , Dilip K. Banerji Shrubbery: A New Algorithm for Quickly Growing High-Quality Steiner Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit D. Mediratta , Jeff Sondeen , Jeffrey T. Draper An Area-Efficient Router for the Data-Intensive Architecture (DIVA) System. [Citation Graph (0, 0)][DBLP ] Conf ] PariVallal Kannan , Dinesh Bhatia Estimating Pre-Placement FPGA Interconnection Requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Rajat Gupta Digital Design: The components of a new paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Dong Hyun Baik , Kewal K. Saluja , Seiji Kajihara Random Access Scan: A solution to test power, test data volume and test time. [Citation Graph (0, 0)][DBLP ] Conf ] Sagar S. Sabade , D. M. H. Walker Comparison of Effectiveness of Current Ratio and Delta-IDDQ Tests. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaogang Du , Sudhakar M. Reddy , Wu-Tung Cheng , Joseph Rayhawk , Nilanjan Mukherjee At-Speed Built-in Self-Repair Analyzer for Embedded Word-Oriented Memories. [Citation Graph (0, 0)][DBLP ] Conf ] M. S. Gaur , Mark Zwolinski Integrating Self Testability with Design Space Exploration by a Controller based Estimation Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Gethin Norman , David Parker , Marta Z. Kwiatkowska , Sandeep K. Shukla Evaluating the Reliability of Defect-Tolerant Architectures for Nanotechnology with Probabilistic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Chandra Shekhar , Raj Singh , A. S. Mandal , S. C. Bose , Ravi Saini , Pramod Tanwar Application Specific Instruction Set Processors: Redefining Hardware-Software Boundary. [Citation Graph (0, 0)][DBLP ] Conf ] Prabhat Mishra , Arun Kejariwal , Nikil Dutt Synthesis-driven Exploration of Pipelined Embedded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] S. Chakraverty Cosynthesis of multiprocessor architectures with high availability. [Citation Graph (0, 0)][DBLP ] Conf ] Virendra Singh , Michiko Inoue , Kewal K. Saluja , Hideo Fujiwara Instruction-Based Delay Fault Self-Testing of Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Ramesh Harjani , Jackson Harvey , Robert Sainati Analog/RF Physical Layer Issues For UWB Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Arijit Mukhopadhyay , Saptarshi Biswas , Pratik Worah , Ramasish Das , Susmit Biswas , Anupam Basu Katha-Mala: A Voice Output Communication Aid for the Children with Severe Speech and Multiple Disorders (SSMI). [Citation Graph (0, 0)][DBLP ] Conf ] Amit Gupta , Steven P. Levitan , Leo Selavo , Donald M. Chiarulli High-Speed Optoelectronics Receivers in SiGe. [Citation Graph (0, 0)][DBLP ] Conf ] Stelian Alupoaei , Srinivas Katkoori Ant Colony Optimization Technique for Macrocell Overlap Removal. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Feng , Dinesh P. Mehta Constrained Floorplanning with Whitespace. [Citation Graph (0, 0)][DBLP ] Conf ] Kun Gao , Dinesh P. Mehta Floorplan Classification Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Anbalagan , Jeffrey A. Davis Maximum Multiplicity Distributions for Length Prediction Driven Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Shabbir H. Batterywala , Narendra V. Shenoy Computing Silent Gate Models for Noise Analysis from Slew and Delay Tables. [Citation Graph (0, 0)][DBLP ] Conf ] Rohan Mandrekar , Madhavan Swaminathan , Sungjun Chun Application of Wavelets and Generalized Pencil-Of-Function Method for the Extraction of Noise Current Spectrum and Simulation of Simultaneous Switching Noise. [Citation Graph (0, 0)][DBLP ] Conf ] Li Ding 0002 , Pinaki Mazumder Dynamic Noise Margin: Definitions and Model. [Citation Graph (0, 0)][DBLP ] Conf ] Richard McCartney , Nikhil Balram Advanced LCD Timing Controller IC with Memory-Assisted Response Time Compensation. [Citation Graph (0, 0)][DBLP ] Conf ] Sasikumar Cherubal , Ramakrishna Voorakaranam , Abhijit Chatterjee , John McLaughlin , Jason L. Smith , David M. Majernik Concurrent RF Test Using Optimized Modulated RF Stimuli. [Citation Graph (0, 0)][DBLP ] Conf ] Antonija Soldo , Anand Gopalan , P. R. Mukund , Martin Margala A Current Sensor for On-Chip, Non-Intrusive Testing of RF Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sunil Rafeeque , Vinita Vasudevan A Built-in-Self-Test Scheme for Digital to Analog Converters. [Citation Graph (0, 0)][DBLP ] Conf ] Tezaswi Raja , Vishwani D. Agrawal , Michael L. Bushnell CMOS Circuit Design for Minimum Dynamic Power and Highest Speed. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Zhong , Niraj K. Jha Dynamic Power Optimization of Interactive Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaus Voß , Bärbel Mertsching A Framework for Low Power Audio Design. [Citation Graph (0, 0)][DBLP ] Conf ] T. K. Priya , K. Sridharan An Efficient Algorithm to Construct Reduced Visibility Graph and Its FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Saraju P. Mohanty , Nagarajan Ranganathan , Ravi Namballa VLSI Implementation of Visible Watermarking for a Secure Digital Still Camera Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kavish Seth , P. Rangarajan , S. Srinivasan , V. Kamakoti , V. Bala Kuteshwar A Parallel Architectural Implementation Of The New Three-Step Search Algorithm For Block Motion Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] J. Lee , Narayanan Vijaykrishnan , Mary Jane Irwin , Wayne Wolf An Architecture for Motion Estimation in the Transform Domain. [Citation Graph (0, 0)][DBLP ] Conf ] Aleksandar Beric , Ramanathan Sethuraman , Harm Peters , Jef L. van Meerbergen , Gerard de Haan , Carlos A. Alba Pinto A 27 mW 1.1 mm2 Motion Estimator for Picture-Rate Up-converter. [Citation Graph (0, 0)][DBLP ] Conf ] 