Conferences in DBLP
(recosoc) Katarina Paulsson , Michael Hübner , Salih Bayar , Jürgen Becker Exploitation of Run-Time Partial Reconfiguration for Dynamic Power Management in Xilinx Spartan III-based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , Andre Guntoro , Heiko Hinkelmann , P. B. Bacinschi , Manfred Glesner Low-Complexity Adaptive Encoding Schemes Based on Partial Bus-Invert for Power Reduction in Buses Exhibiting Capacitive Coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Hoogvorst , Sylvain Guilley , Sumanta Chau , Alin Razafindraibe , Taha Beyrouthy , Laurent Fesquet A Reconfigurable Cell for a Multi-Style Asynchronous FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Leandro Möller , Ismael Grehs , Ewerson Carvalho , Rafael Soares , Ney Calazans , Fernando Moraes A NoC-based Infrastructure to Enable Dynamic Self Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marcelo Götz , Tao Xie , Florian Dittmann Dynamic Relocation of Hybrid Tasks: A Complete Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Saint-Jean , Camille Jalier , Gilles Sassatelli , Pascal Benoit , Lionel Torres , Michel Robert HS Scale: A run-time adaptable MP-SoC architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Kurt Franz Ackermann , Leandro Soares Indrusiak , Manfred Glesner System Level Design of a Dynamically Self-Reconfigurable Image Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zipf , Heiko Hinkelmann , Felix Missel , Manfred Glesner A Customizable LEON2-Based VLIW Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Hritam Dutta , Frank Hannig , Alexey Kupriyanov , Dmitrij Kissler , Jürgen Teich , Rainer Schaffer , Sebastian Siegel , Renate Merker , Bernard Pottier Massively Parallel Processor Architectures: A Co-design Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Mehdi Jallouli , Camille Diou , Fabrice Monteiro Stack processor architecture and development methods suitable for dependable applications. [Citation Graph (0, 0)][DBLP ] Conf ] Samar Yazdani , Joel Cambonie , Bernard Pottier Coordinated concurrent memory accesses on a reconfigurable multimedia processor. [Citation Graph (0, 0)][DBLP ] Conf ] Sanna Määttä , Jari Nurmi Experiences of Using Object Oriented Programming Methods in High Level Network-on-Chip and System-on-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Sébastien Le Beux , Philippe Marquet , Jean-Luc Dekeyser Multiple Abstraction Views of FPGA to Map Parallel Applications. [Citation Graph (0, 0)][DBLP ] Conf ] S. Jovanovic , Camel Tanougast , Christophe Bobda , Serge Weber A Dynamic Communication Structure for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Haller , Christophe Bobda Adaptive Network for Multiprocessing in Programmable Logic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Antoine Scherrer , Antoine Fraboulet , Tanguy Risset Long-Range Dependence and On-chip Processor Traffic. [Citation Graph (0, 0)][DBLP ] Conf ] Brendan Mullane , Chen-Huan Chiang , Michael Higgins , Ciaran MacNamee , Tapan J. Chakraborty , Thomas B. Cook FPGA Prototyping of a Scan Based System-On-Chip Design. [Citation Graph (0, 0)][DBLP ] Conf ] Anatol Ursu Latch Inference for Equivalence Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgio Di Natale , Marie-Lise Flottes , Bruno Rouzeyre A Dependable Parallel Architecture for SBoxes. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo Wanderley Neto , Reouven Elbaz , Lionel Torres , Gilles Sassatelli , Romain Vaslin , Guy Gogniat , Jean-Philippe Diguet IBC-EI: An Instruction Based Compression method with Encryption and Integrity Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Romain Vaslin , Guy Gogniat , Eduardo Wanderley Neto , Russell Tessier , Wayne P. Burleson Low latency Solution for Confidentiality and Integrity Checking in Embedded Systems with Off-Chip Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Ferrante , Antonio Vincenzo Taddeo , Mariagiovanna Sami , Fabrizio Mantovani , Jurijs Fridkins Self-adaptive Security at Application Level: a Proposal. [Citation Graph (0, 0)][DBLP ] Conf ] Hervé Berviller , Vincent Frick , Philippe Bougeot , Jean-Philippe Blonde , Julien Oster , Jacques Felbinger FPGA Implemenatation of an Adaptive Filtering: Application on ECG Signal Artefact Suppression in MRI Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Fabio Garzia , Claudio Brunelli , Andrea Ferro , Jari Nurmi Implementation of a 2D low-pass image filtering algorithm on a reconfigurable device. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Alberto Vite-Frias , René de Jesús Romero-Troncoso , Alejandro Ordaz-Moreno , Jesus Rooney Rivera-Guillen , Arturo Garcia-Perez Special Purpose Multi-processor for On-line Fault Detection on Induction Motors during Steady State. [Citation Graph (0, 0)][DBLP ] Conf ] J. Liu , Ian O'Connor , David Navarro , Frédéric Gaffiot A Family of Ultra-Fine Grain CNTFET-based Reconfigurable Logic Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Hinkelmann , Tudor Murgan , G. Liu , Peter Zipf , Manfred Glesner On the Design of a Reconfigurable Multiplier for Integer and Galois Field Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Haller , José Rodrigo Azambuja , Christophe Bobda Automatic Generation of Adaptive Multiprocessor Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jesus Rooney Rivera-Guillen , René de Jesús Romero-Troncoso , Alejandro Ordaz-Moreno , Jose Alberto Vite-Frias Dedicated Multiprocessing Unit for Polynomial Evaluation on FPGA in CNC Profile Generation. [Citation Graph (0, 0)][DBLP ] Conf ] Alejandro Ordaz-Moreno , René de Jesús Romero-Troncoso , Jose Alberto Vite-Frias , Jesus Rooney Rivera-Guillen , Arturo Garcia-Perez Dedicated Special Purpose Multiprocessor System for the Diagnostic of Rotor Bar Breakage on Induction Motors. [Citation Graph (0, 0)][DBLP ] Conf ] Wladyslaw Szczesniak Selecting the Optimal Number of Functional Units of Digital Real Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] 