Conferences in DBLP
Dan C. Marinescu Quantum parallelism and the exact simulation of physical systems. [Citation Graph (0, 0)][DBLP ] Conf ] G. Rossi , E. Poleo javaset: declarative programming in Java with sets. [Citation Graph (0, 0)][DBLP ] Conf ] Takahiro Katagiri , Kenji Kise , Hiroki Honda , Toshitsugu Yuba Effect of auto-tuning with user's knowledge for numerical software. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslaw Malek Introduction to NOMADS: networks of mobile adaptive dependable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Casimiro , Jörg Kaiser , Paulo Veríssimo An architectural framework and a middleware for cooperating smart components. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar Nett , Stefan Schemmer An architecture to support cooperating mobile embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Stefano Porcarelli , Felicita Di Giandomenico , Andrea Bondavalli , Paolo Lollini Model-based evaluation of a radio resource management system for wireless networks. [Citation Graph (0, 0)][DBLP ] Conf ] Girma Berhe , Lionel Brunie , Jean-Marc Pierson Modeling service-based multimedia content adaptation in pervasive computing. [Citation Graph (0, 0)][DBLP ] Conf ] K. Kalapriya , S. K. Nandy , Deepti Srinivasan , R. Uma Maheshwari , V. Satish A framework for resource discovery in pervasive computing for mobile aware task execution. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Negri , Domenico Barretta , William Fornaciari Application-level power management in pervasive computing systems: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Sándor Imre , Péter Abronits , Dániel Darabos Quantum designer and network simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Mihai Udrescu , Lucian Prodan , Mircea Vladutiu Using HDLs for describing quantum circuits: a framework for efficient quantum algorithm simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Jorrand , Marie Lalire Toward a quantum process algebra. [Citation Graph (0, 0)][DBLP ] Conf ] Marion G. Ceruti States of matter, information organization and dimensions of expressiveness. [Citation Graph (0, 0)][DBLP ] Conf ] Frédéric Gruau , Yves Lhuillier , Philippe Reitz , Olivier Temam BLOB computing. [Citation Graph (0, 0)][DBLP ] Conf ] E. V. Krishnamurthy , Venu K. Murthy , Vikram Krishnamurthy Biologically inspired rule-based multiset programming paradigm for soft-computing. [Citation Graph (0, 0)][DBLP ] Conf ] Liliana Cojocaru Watson-Crick automata and PCFAS with two components: a computational power analogy. [Citation Graph (0, 0)][DBLP ] Conf ] Sally A. McKee Reflections on the memory wall. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Dubois Fighting the memory wall with assisted execution. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Kämpe , Per Stenström , Michel Dubois Self-correcting LRU replacement policies. [Citation Graph (0, 0)][DBLP ] Conf ] Ben H. H. Juurlink , Pepijn J. de Langen Dynamic techniques to reduce memory traffic in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Antonis Papanikolaou , Miguel Miranda , Francky Catthoor Overcoming the "Memory Wall" by improved system design exploration and a link to process technology options. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Galluzzi , Valentin Puente , Adrián Cristal , Ramón Beivide , José-Ángel Gregorio , Mateo Valero A first glance at Kilo-instruction based multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Keqiang Wu , Peng-fei Chuang , David J. Lilja An active data-aware cache consistency protocol for highly-scalable data-shipping DBMS architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Pepijn J. de Langen , Ben H. H. Juurlink Reducing traffic generated by conflict misses in caches. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh Chheda , Osman S. Unsal , Israel Koren , C. Mani Krishna , Csaba Andras Moritz Combining compiler and runtime IPC predictions to reduce energy in next generation architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Christopher R. LaRosa , Mark W. Bailey A docked-aware storage architecture for mobile computing. [Citation Graph (0, 0)][DBLP ] Conf ] Gábor Németh Knowledge-based generic intelligent network model. [Citation Graph (0, 0)][DBLP ] Conf ] Iliyak Georgiev , Ivo I. Georgiev An information-interconnectivity-based retrieval method for network attached storage. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Kühnemann , Thomas Rauber , Gudula Rünger Improving the execution time of global communication operations. [Citation Graph (0, 0)][DBLP ] Conf ] Ambrus Wagner Mobile agent: based module distribution in heterogeneous networks. [Citation Graph (0, 0)][DBLP ] Conf ] Micaela Spigarolo , Renzo Davoli Berserkr: a virtual beowulf cluster for fast prototyping and teaching. [Citation Graph (0, 0)][DBLP ] Conf ] Michal Kouril , Jerome L. Paul A parallel backtracking framework (BkFr) for single and multiple clusters. [Citation Graph (0, 0)][DBLP ] Conf ] Ben H. H. Juurlink Approximating the optimal replacement algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] M. Francia , E. Panizzi , A. Petricola , G. Visconti Parallel simulation of orography influence on large-scale atmosphere motion on APEmille. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Bera , Giovanni Danese , Francesco Leporati , Alvaro Spelgatti A new technique to calculate dipolar energy and its implementation onto an application specific processor. [Citation Graph (0, 0)][DBLP ] Conf ] Yong-Joon Park , Gyungho Lee Repairing return address stack for buffer overflow protection. [Citation Graph (0, 0)][DBLP ] Conf ] Nozar Tabrizi , Nader Bagherzadeh , Amir Hosein Kamalizad , Haitao Du MaRS: a macro-pipelined reconfigurable system. [Citation Graph (0, 0)][DBLP ] Conf ] T. Feng , Byoungjae Jin , J. Wang , Nohpill Park , Yong-Bin Kim , Fabrizio Lombardi Fault tolerant clockless wave pipeline design. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein The digital divide of computing. [Citation Graph (0, 0)][DBLP ] Conf ] Ingrid Verbauwhede , Patrick Schaumont The happy marriage of architecture and application in next-generation reconfigurable systems. [Citation Graph (0, 0)][DBLP ] Conf ] Manfred Glesner , Thomas Hollstein , Leandro Soares Indrusiak , Peter Zipf , Thilo Pionteck , Mihail Petrov , Heiko Zimmer , Tudor Murgan Reconfigurable platforms for ubiquitous computing. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Reis , Fernanda Lima Kastensmidt , José Luís Almada Güntzel Physical design methodologies for performance predictability and manufacturability. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Koch , Jürgen Teich Platform-independent methodology for partial reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Murgan , Mihail Petrov , Mateusz Majer , Peter Zipf , Manfred Glesner , Ulrich Heinkel , Jörg Pleickhardt , Bernd Bleisteiner Adaptive architectures for an OTN processor: reducing design costs through reconfigurability and multiprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] Fernanda Lima Kastensmidt , Gustavo Neuberger , Luigi Carro , Ricardo Reis Designing and testing fault-tolerant techniques for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco J. Cazorla , Peter M. W. Knijnenburg , Rizos Sakellariou , Enrique Fernández , Alex Ramírez , Mateo Valero Predictable performance in SMT processors. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , T. M. Mak , Martin Omaña Fault secureness need for next generation high performance microprocessor design for testability structures. [Citation Graph (0, 0)][DBLP ] Conf ] X. H. Xu , C. T. Clarke , S. R. Jones High performance code compression architecture for the embedded ARM/THUMB processor. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul Nagpal , Y. N. Srikant Integrated temporal and spatial scheduling for extended operand clustered VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Groen , Panu Hämäläinen , Ben H. H. Juurlink , Timo Hämäläinen Accelerating the secure remote password protocol using reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Atsushi Kosaka , Satoshi Yamaguchi , Hiroyuki Okuhata , Takao Onoye , Isao Shirakawa SoC design of Ogg Vorbis decoder using embedded processor. [Citation Graph (0, 0)][DBLP ] Conf ] Predrag T. Tosic A perspective on the future of massively parallel computing: fine-grain vs. coarse-grain parallel models comparison & contrast. [Citation Graph (0, 0)][DBLP ] Conf ] Teng Wang , Zhenghua Qi , Csaba Andras Moritz Opportunities and challenges in application-tuned circuits and architectures based on nanodevices. [Citation Graph (0, 0)][DBLP ] Conf ] 