Conferences in DBLP
Pai H. Chou , Gaetano Borriello An analysis-based approach to composition of distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Ziegenbein , Rolf Ernst , Kai Richter , Jürgen Teich , Lothar Thiele Combining multiple models of computation for scheduling and allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio Passerone , Roberto Passerone , Claudio Sansoè , Jonathan Martin , Alberto L. Sangiovanni-Vincentelli , Rick McGeer Modeling reactive systems in Java. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Henkel , Yanbing Li Energy-conscious HW/SW-partitioning of embedded systems: a case study on an MPEG-2 encoder. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Hollstein , Jürgen Becker , Andreas Kirschbaum , Manfred Glesner HiPART: a new hierarchical semi-interactive HW-/SW partitioning approach with fast debugging for real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Franz Fischer , Annette Muth , Georg Färber Towards interprocess communication and interface synthesis for a heterogeneous real-time rapid prototyping environment. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Eisenring , Jürgen Teich Domain-specific interface generation from dataflow specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Guy Gogniat , Michel Auguin , Luc Bianco , Alain Pegatoquet Communication synthesis and HW/SW integration for embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Voigt Knudsen , Jan Madsen Communication estimation for hardware/software codesign. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Liu , Marcello Lajolo , Alberto L. Sangiovanni-Vincentelli Software timing analysis using HW/SW cosimulation and instruction set simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Sungjoo Yoo , Kiyoung Choi Optimistic distributed timed cosimulation based on thread simulation model. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe Del Castillo , Wolfram Hardt Fast dynamic analysis of complex HW/SW-systems based on abstract state machine models. [Citation Graph (0, 0)][DBLP ] Conf ] Luc Bianco , Michel Auguin , Guy Gogniat , Alain Pegatoquet A path analysis based partitioning for time constrained embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Slomka , Jürgen Zant , Lennard Lambert Schedulability analysis of heterogeneous systems for performance message sequence chart. [Citation Graph (0, 0)][DBLP ] Conf ] Robert P. Dick , David L. Rhodes , Wayne Wolf TGFF: task graphs for free. [Citation Graph (0, 0)][DBLP ] Conf ] Josef Fleischmann , Klaus Buchenrieder , Rainer Kress A hardware/software prototyping environment for dynamically reconfigurable embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Marc Daveau , Gilberto Fernandes Marchioro , Ahmed Amine Jerraya Hardware/software co-design of an ATM network interface card: a case study. [Citation Graph (0, 0)][DBLP ] Conf ] Marcello Lajolo , Anand Raghunathan , Sujit Dey , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli A case study on modeling shared memory access effects during performance analysis of HW/SW systems. [Citation Graph (0, 0)][DBLP ] Conf ] Bart Kienhuis , Ed F. Deprettere , Kees A. Vissers , Pieter van der Wolf The construction of a retargetable simulator for an architecture template. [Citation Graph (0, 0)][DBLP ] Conf ] Jian Li , Rajesh K. Gupta HDL code restructuring using timed decision tables. [Citation Graph (0, 0)][DBLP ] Conf ] Karam S. Chatha , Ranga Vemuri RECOD: a retiming heuristic to optimize resource and memory utilization in HW/SW codesigns. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Grun , Florin Balasa , Nikil D. Dutt Memory size estimation for multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] 