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Conferences in DBLP
- Sreeranga P. Rajan, Masahiro Fujita, Ashok Sudarsanam, Sharad Malik
Development of an optimizing compiler for a Fujitsu fixed-point digital signal processor. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:2-6 [Conf]
- Michael Gschwind
Instruction set selection for ASIP design. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:7-11 [Conf]
- Margarida F. Jacome, Gustavo de Veciana, Cagdas Akturan
Resource constrained dataflow retiming heuristics for VLIW ASIPs. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:12-16 [Conf]
- Kayhan Küçükçakar
An ASIP design methodology for embedded systems. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:17-21 [Conf]
- Marnix Arnold, Henk Corporaal
Automatic detection of recurring operation patterns. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:22-26 [Conf]
- François Charot, Vincent Messé
A flexible code generation framework for the design of application specific programmable processors. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:27-31 [Conf]
- Pieter van der Wolf, Paul Lieverse, Mudit Goel, David La Hei, Kees A. Vissers
An MPEG-2 decoder case study as a driver for a system level design methodology. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:33-37 [Conf]
- Dirk Desmet, Michiel Esvelt, Prabhat Avasare, Diederik Verkest, Hugo De Man
Timed executable system specification of an ADSL modem using a C++ based design environment: a case study. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:38-42 [Conf]
- Tomás Bautista, Antonio Núñez
Flexible design of SPARC cores: a quantitative study. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:43-47 [Conf]
- François Clouté, Jean-Noël Contensou, Daniel Esteve, Pascal Pampagnin, Philippe Pons, Yves Favard
Hardware/software co-design of an avionics communication protocol interface system: an industrial case study. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:48-52 [Conf]
- P. Coste, F. Hessel, P. LeMarrec, Zoltan Sugar, M. Romdhani, Rodolph Suescun, Nacer-Eddine Zergainoh, Ahmed Amine Jerraya
Multilanguage design of heterogeneous systems. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:54-58 [Conf]
- Frank Vahid, Tony Givargis
The case for a configure-and-execute paradigm. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:59-63 [Conf]
- H. J. H. N. Kenter, Claudio Passerone, W. J. M. Smits, Yosinori Watanabe, Alberto L. Sangiovanni-Vincentelli
Designing digital video systems: modeling and scheduling. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:64-68 [Conf]
- François Pogodalla, Richard Hersemeule, Pierre Coulomb
Fast prototyping: a system design flow for fast design, prototyping and efficient IP reuse. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:69-73 [Conf]
- Thierry Grandpierre, Christophe Lavarenne, Yves Sorel
Optimized rapid prototyping for real-time embedded heterogeneous multiprocessors. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:74-78 [Conf]
- Francis G. Wolff, Michael J. Knieser, Daniel J. Weyer, Christos A. Papachristou
Using codesign techniques to support analog functionality. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:79-84 [Conf]
- Marcello Lajolo, Mihai Lazarescu, Alberto L. Sangiovanni-Vincentelli
A compilation-based software estimation scheme for hardware/software co-simulation. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:85-89 [Conf]
- Tao Zhou, Xiaobo Sharon Hu, Edwin Hsing-Mean Sha
A probabilistic performance metric for real-time system design. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:90-94 [Conf]
- Zhao Wu, Wayne Wolf
Iterative cache simulation of embedded CPUs with trace stripping. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:95-99 [Conf]
- Sungjoo Yoo, Kiyoung Choi
Optimizing geographically distributed timed cosimulation by hierarchically grouped messages. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:100-104 [Conf]
- Donald E. Thomas, JoAnn M. Paul, Simon N. Peffers, Sandra J. Weber
Peer-based multithreaded executable co-specification. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:105-109 [Conf]
- Pao-Ann Hsiung
Timing coverification of concurrent embedded real-time systems. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:110-114 [Conf]
- Felice Balarin
Worst-case analysis of discrete systems based on conditional abstractions. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:115-119 [Conf]
- Jianwen Zhu, Daniel Gajski
A unified formal model of ISA and FSMD. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:121-125 [Conf]
- Ansgar Bredenfeld
Co-design tool construction using APICES. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:126-130 [Conf]
- Peter Voigt Knudsen, Jan Madsen
Graph based communication analysis for hardware/software codesign. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:131-135 [Conf]
- Ingo Sander, Axel Jantsch
System synthesis utilizing a layered functional model. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:136-140 [Conf]
- Jean-Yves Brunel, Erwin A. de Kock, W. M. Kruijtzer, H. J. H. N. Kenter, W. J. M. Smits
Communication refinement in video systems on chip. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:142-146 [Conf]
- Stephen A. Edwards
Compiling Esterel into sequential code. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:147-151 [Conf]
- William Fornaciari, Donatella Sciuto, Cristina Silvano
Power estimation for architectural exploration of HW/SW communication on system-level buses. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:152-156 [Conf]
- Yung-Hsiang Lu, Tajana Simunic, Giovanni De Micheli
Software controlled power management. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:157-161 [Conf]
- I. D. Bates, E. Graeme Chester, D. J. Kinniment
A statechart based HW/SW codesign system. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:162-166 [Conf]
- Jürgen Teich, Eckart Zitzler, Shuvra S. Bhattacharyya
3D exploration of software schedules for DSP algorithms. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:168-172 [Conf]
- Karsten Strehl, Lothar Thiele, Dirk Ziegenbein, Rolf Ernst, Jürgen Teich
Scheduling hardware/software systems using symbolic techniques. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:173-177 [Conf]
- Paul Pop, Petru Eles, Zebo Peng
Scheduling with optimized communication for time-triggered embedded systems. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:178-182 [Conf]
- Hyunok Oh, Soonhoi Ha
A hardware-software cosynthesis technique based on heterogeneous multiprocessor scheduling. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:183-187 [Conf]
- Jan Madsen, Peter Bjørn-Jørgensen
Embedded system synthesis under memory constraints. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:188-192 [Conf]
- David L. Rhodes, Wayne Wolf
Overhead effects in real-time preemptive schedules. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:193-197 [Conf]
- Jones Albuquerque, Claudionor José Nunes Coelho Jr., Carlos Frederico Cavalcanti, Diógenes Cecilio da Silva Jr., Antônio Otávio Fernandes
System-level partitioning with uncertainty. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:198-202 [Conf]
- Dinesh Ramanathan, Ali Dasdan, Rajesh K. Gupta
Timing-driven HW/SW codesign based on task structuring and process timing simulation. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:203-207 [Conf]
- Jonas Plantin, Erik Stoy
Aspects of system-level design. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:209-210 [Conf]
- Mark Genoe, Christopher K. Lennard, Joachim Kunkel, Brian Bailey, Gjalt G. de Jong, Grant Martin, M. M. Kamal Hashmi, Shay Ben-Chorin, Anssi Haverinen
How standards will enable hardware/software co-design. [Citation Graph (0, 0)][DBLP]
CODES, 1999, pp:211-212 [Conf]
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