Conferences in DBLP
Jay Vleeschhouwer , Warren East , Michael J. Fister , Aart J. de Geus , Walden C. Rhines , Jackson Hu , Rick Cassidy Differentiate and deliver: leveraging your partners. [Citation Graph (0, 0)][DBLP ] Conf ] Subhasish Mitra , Tanay Karnik , Norbert Seifert , Ming Zhang Logic soft errors in sub-65nm technologies design and CAD challenges. [Citation Graph (0, 0)][DBLP ] Conf ] William Heidergott SEU tolerant device, circuit and processor design. [Citation Graph (0, 0)][DBLP ] Conf ] Diana Marculescu , Emil Talpes Variability and energy awareness: a microarchitecture-level perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Petrov , Daniel Tracy , Alex Orailoglu Energy-effcient physically tagged caches for embedded processors with virtual memory. [Citation Graph (0, 0)][DBLP ] Conf ] Anish Muttreja , Anand Raghunathan , Srivaths Ravi , Niraj K. Jha Hybrid simulation for embedded software energy estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Schaumont , Bo-Cheng Charles Lai , Wei Qin , Ingrid Verbauwhede Cooperative multithreading on 3mbedded multiprocessor architectures enables energy-scalable design. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Gao , John P. Hayes Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Farzan Fallah , Massoud Pedram An effective power mode transition technique in MTCMOS circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Jayakumar , Sandeep Dhar , Sunil P. Khatri A self-adjusting scheme to determine the optimum RBB by monitoring leakage currents. [Citation Graph (0, 0)][DBLP ] Conf ] Lin Yuan , Gang Qu Enhanced leakage reduction Technique by gate replacement. [Citation Graph (0, 0)][DBLP ] Conf ] Ning Dong , Jaijeet S. Roychowdhury Automated nonlinear Macromodelling of output buffers for high-speed digital applications. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Wei , Alex Doboli Systematic development of analog circuit structural macromodels through behavioral model decoupling. [Citation Graph (0, 0)][DBLP ] Conf ] Mengmeng Ding , Ranga Vemuri A combined feasibility and performance macromodel for analog circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , David Maliniak , Terry Doherty , Peter McShane , Suhas A. Pai , Sriram Sundararajan , Soo-Kwan Eo , Pascal Urard ESL: building the bridge between systems to silicon. [Citation Graph (0, 0)][DBLP ] Conf ] Hongliang Chang , Vladimir Zolotov , Sambasivan Narayan , Chandu Visweswariah Parameterized block-based statistical timing analysis with non-gaussian parameters, nonlinear delay functions. [Citation Graph (0, 0)][DBLP ] Conf ] Yaping Zhan , Andrzej J. Strojwas , Xin Li , Lawrence T. Pileggi , David Newmark , Mahesh Sharma Correlation-aware statistical timing analysis with non-gaussian delay distributions. [Citation Graph (0, 0)][DBLP ] Conf ] Lizheng Zhang , Weijen Chen , Yuhen Hu , John A. Gubner , Charlie Chung-Ping Chen Correlation-preserved non-gaussian statistical timing analysis with quadratic timing model. [Citation Graph (0, 0)][DBLP ] Conf ] Vishal Khandelwal , Ankur Srivastava A general framework for accurate statistical timing analysis considering correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Feihui Li , Mahmut T. Kandemir Locality-conscious workload assignment for array-based computations in MPSOC architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Valentin Gheorghita , Sander Stuijk , Twan Basten , Henk Corporaal Automatic scenario detection for improved WCET estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Jungeun Kim , Taewhan Kim Memory access optimization through combined code scheduling, memory allocation, and array binding in embedded system design. [Citation Graph (0, 0)][DBLP ] Conf ] Ravindra Jejurikar , Rajesh K. Gupta Dynamic slack reclamation with procrastination scheduling in real-time embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Erik H. Volkerink , Subhasish Mitra Response compaction with any number of unknowns using a new LFSR architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Xu , Nicola Nicolici , Krishnendu Chakrabarty Multi-frequency wrapper design and optimization for embedded cores under average power constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz N-detection under transparent-scan. [Citation Graph (0, 0)][DBLP ] Conf ] Bo Yang , Kaijie Wu , Ramesh Karri Secure scan: a design-for-test architecture for crypto chips. [Citation Graph (0, 0)][DBLP ] Conf ] Chenggang Xu , Ranjit Gharpurey , Terri S. Fiez , Kartikeya Mayaram A green function-based parasitic extraction method for inhomogeneous substrate layers. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Hu , Jung Hoon Lee , Jacob White , Luca Daniel Analysis of full-wave conductor system impedance over substrate using novel integration techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Michael W. Beattie , Hui Zheng , Anirudh Devgan , Byron Krauter Spatially distributed 3D circuit models. [Citation Graph (0, 0)][DBLP ] Conf ] Dipanjan Gope , Indranil Chowdhury , Vikram Jandhyala DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Jiang , Yi-Hao Chang , Charlie Chung-Ping Chen ICCAP: a linear time sparse transformation and reordering algorithm for 3D BEM capacitance extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Dennis Wassung , Yervant Zorian , Magdy S. Abadir , Mark Bapst , Colin Harris Choosing flows and methodologies for SoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Naveed A. Sherwani , Susan Lippincott Mack , Alex Alexanian , Premal Buch , Carlo Guardiani , Harold Lehon , Peter Rabkin , Atul Sharan DFM rules! [Citation Graph (0, 0)][DBLP ] Conf ] Hang Li , Zhenyu Qi , Sheldon X.-D. Tan , Lifeng Wu , Yici Cai , Xianlong Hong Partitioning-based approach to fast on-chip decap budgeting and minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Yongqiang Lu , Cliff C. N. Sze , Xianlong Hong , Qiang Zhou , Yici Cai , Liang Huang , Jiang Hu Navigating registers in placement for clock network minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Yow-Tyng Nieh , Shih-Hsu Huang , Sheng-Yu Hsu Minimizing peak current via opposite-phase clock tree. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Su , David Widiger , Chandramouli V. Kashyap , Frank Liu , Byron Krauter A noise-driven effective capacitance method with fast embedded noise rule calculation for functional noise analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Chong Zhao , Yi Zhao , Sujit Dey Constraint-aware robustness insertion for optimal noise-tolerance enhancement in VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Seda Ogrenci Memik , Gokhan Memik Temperature-aware resource allocation and binding in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoyong Tang , Hai Zhou , Prithviraj Banerjee Leakage power optimization with dual-Vth library in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Zhenyu (Peter) Gu , Jia Wang , Robert P. Dick , Hai Zhou Incremental exploration of the combined physical and behavioral design space. [Citation Graph (0, 0)][DBLP ] Conf ] M. Saneei , Ali Afzali-Kusha , Zainalabedin Navabi Sign bit reduction encoding for low power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Tingyuan Nie , Tomoo Kisaka , Masahiko Toyonaga A watermarking system for IP protection by a post layout incremental router. [Citation Graph (0, 0)][DBLP ] Conf ] Kris Tiri , David Hwang , Alireza Hodjat , Bo-Cheng Lai , Shenglin Yang , Patrick Schaumont , Ingrid Verbauwhede A side-channel leakage free coprocessor IC in 0.18µm CMOS for embedded AES-based cryptographic and biometric processing. [Citation Graph (0, 0)][DBLP ] Conf ] Kris Tiri , Ingrid Verbauwhede Simulation models for side-channel information leaks. [Citation Graph (0, 0)][DBLP ] Conf ] Young H. Cho , William H. Mangione-Smith A pattern matching coprocessor for network security. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Balderas-Contreras , René Cumplido High performance encryption cores for 3G networks. [Citation Graph (0, 0)][DBLP ] Conf ] Pallav Gupta , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Efficient fingerprint-based user authentication for embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Yanhong Liu , Samarjit Chakraborty , Wei Tsang Ooi Approximate VCCs: a new characterization of multimedia workloads for system-level MpSoC design. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Sauer , Matthias Gries , Sören Sonntag Modular domain-specific implementation and exploration framework for embedded software platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Xi Chen , Abhijit Davare , Harry Hsieh , Alberto L. Sangiovanni-Vincentelli , Yosinori Watanabe Simulation based deadlock analysis for system level designs. [Citation Graph (0, 0)][DBLP ] Conf ] Sorin Manolache , Petru Eles , Zebo Peng Fault and energy-aware communication mapping with guaranteed latency for applications implemented on NoC. [Citation Graph (0, 0)][DBLP ] Conf ] Andrey V. Zykov , Elias Mizan , Margarida F. Jacome , Gustavo de Veciana , Ajay Subramanian High performance computing on fault-prone nanotechnologies: novel microarchitecture techniques exploiting reliability-delay trade-offs. [Citation Graph (0, 0)][DBLP ] Conf ] Nic Mokhoff , Yervant Zorian , Kamalesh N. Ruparel , Hao Nham , Francesco Pessolano , Kee Sup Kim How to determine the necessity for emerging solutions. [Citation Graph (0, 0)][DBLP ] Conf ] David G. Chinnery , Kurt Keutzer Closing the power gap between ASIC and custom: an ASIC perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Chang , William J. Dally Explaining the gap between ASIC and custom power: a custom perspective. [Citation Graph (0, 0)][DBLP ] Conf ] Ruchir Puri , Leon Stok , Subhrajit Bhattacharya Keeping hot chips cool. [Citation Graph (0, 0)][DBLP ] Conf ] Navraj Nandra , Phil Dworsky , Rick Merritt , John F. D'Ambrosia , Adam Healey , Boris Litinsky , John Stonick , Joe Abler Interconnects are moving from MHz->GHz should you be afraid?: or... "my giga hertz, does yours?". [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Samuel Chenard , Chun Yiu Chu , Zeljko Zilic , Milica Popovic Design methodology for wireless nodes with printed antennas. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Meng , Andrew P. Brown , Ronald A. Iltis , Timothy Sherwood , Hua Lee , Ryan Kastner MP core: algorithm and design techniques for efficient channel estimation in wireless applications. [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang Eberle , Bruno Bougard , Sofie Pollin , Francky Catthoor From myth to methodology: cross-layer design for energy-efficient wireless communication. [Citation Graph (0, 0)][DBLP ] Conf ] Murari Mani , Anirudh Devgan , Michael Orshansky An efficient algorithm for statistical minimization of total power under timing yield constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Jaskirat Singh , Vidyasagar Nookala , Zhi-Quan Luo , Sachin S. Sapatnekar Robust gate sizing by geometric programming. [Citation Graph (0, 0)][DBLP ] Conf ] Aseem Agarwal , Kaviraj Chopra , David Blaauw , Vladimir Zolotov Circuit optimization using statistical static timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Bor-Yiing Su , Yao-Wen Chang An exact jumper insertion algorithm for antenna effect avoidance/fixing. [Citation Graph (0, 0)][DBLP ] Conf ] Kingshuk Karuri , Mohammad Abdullah Al Faruque , Stefan Kraemer , Rainer Leupers , Gerd Ascheid , Heinrich Meyr Fine-grained application source code profiling for ASIP design. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Banerjee , Elaheh Bozorgzadeh , Nikil D. Dutt Physically-aware HW-SW partitioning for reconfigurable architectures with partial dynamic reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Ho Young Kim , Tag Gon Kim Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse. [Citation Graph (0, 0)][DBLP ] Conf ] Dohyung Kim , Youngmin Yi , Soonhoi Ha Trace-driven HW/SW cosimulation using virtual synchronization technique. [Citation Graph (0, 0)][DBLP ] Conf ] Sani R. Nassif , Paul S. Zuchowski , Claude Moughanni , Mohamed Moosa , Stephen D. Posluszny , Ward Vercruysse The Titanic: what went wrong! [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Jan M. Rabaey , Allan Cox , Frank Lane , Rudy Lauwereins , Ulrich Ramacher , David Witt Wireless platforms: GOPS for cents and MilliWatts. [Citation Graph (0, 0)][DBLP ] Conf ] V. Kheterpal , V. Rovner , T. G. Hersan , D. Motiani , Y. Takegawa , Andrzej J. Strojwas , Lawrence T. Pileggi Design methodology for IC manufacturability based on regular logic-bricks. [Citation Graph (0, 0)][DBLP ] Conf ] Jie Yang , Luigi Capodieci , Dennis Sylvester Advanced timing analysis based on post-OPC extraction of critical dimensions. [Citation Graph (0, 0)][DBLP ] Conf ] Puneet Gupta , Andrew B. Kahng , Youngmin Kim , Dennis Sylvester Advanced Timing Analysis Based on Post-OPC Extraction of Critical Dimensions. [Citation Graph (0, 0)][DBLP ] Conf ] Joydeep Mitra , Peng Yu , David Zhigang Pan RADAR: RET-aware detailed routing using fast lithography simulations. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Munehiro Matsuura BDD representation for incompletely specifiedvmultiple-output logic functions and its applications to functional decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Massoud Pedram A new canonical form for fast boolean matching in logic synthesis and verification. [Citation Graph (0, 0)][DBLP ] Conf ] Xiao Yu Li , Matthias F. M. Stallmann , Franc Brglez Effective bounding techniques for solving unate and binate covering problems. [Citation Graph (0, 0)][DBLP ] Conf ] Yayun Wan , Jaijeet S. Roychowdhury Operator-based model-order reduction of linear periodically time-varying systems. [Citation Graph (0, 0)][DBLP ] Conf ] V. Vasudevan Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Saurabh K. Tiwary , Rob A. Rutenbar Scalable trajectory methods for on-demand analog macromodel extraction. [Citation Graph (0, 0)][DBLP ] Conf ] William Krenik , Anuj Batra Cognitive radio techniques for wide area networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jeffrey M. Gilbert , Won-Joon Choi , Qinfang Sun MIMO technology for advanced wireless local area networks. [Citation Graph (0, 0)][DBLP ] Conf ] Clark T.-C. Nguyen RF MEMS in wireless architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Metzgen , Dominic Nancekievill Multiplexer restructuring for FPGA implementation cost reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew C. Ling , Deshanand P. Singh , Stephen Dean Brown FPGA technology mapping: a study of optimality. [Citation Graph (0, 0)][DBLP ] Conf ] Deshanand P. Singh , Valavan Manohararajah , Stephen Dean Brown Incremental retiming for FPGA physical synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Eguro , Scott Hauck , Akshay Sharma Architecture-adaptive range limit windowing for simulated annealing FPGA placement. [Citation Graph (0, 0)][DBLP ] Conf ] Himanshu Jain , Daniel Kroening , Natasha Sharygina , Edmund M. Clarke Word level predicate abstraction and refinement for verifying RTL verilog. [Citation Graph (0, 0)][DBLP ] Conf ] Ganapathy Parthasarathy , Madhu K. Iyer , Kwang-Ting Cheng , Forrest Brewer Structural search for RTL with predicate learning. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Wedler , Dominik Stoffel , Wolfgang Kunz Normalization at the arithmetic bit level. [Citation Graph (0, 0)][DBLP ] Conf ] Hari Mony , Jason Baumgartner , Viresh Paruthi , Robert Kanzelman Exploiting suspected redundancy without proving it. [Citation Graph (0, 0)][DBLP ] Conf ] Debashis Sahoo , Jawahar Jain , Subramanian K. Iyer , David L. Dill , E. Allen Emerson Multi-threaded reachability. [Citation Graph (0, 0)][DBLP ] Conf ] Grace Nordin , Peter A. Milder , James C. Hoe , Markus Püschel Automatic generation of customized discrete fourier transform IPs. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Hsu Huang , Yow-Tyng Nieh , Feng-Pin Lu Race-condition-aware clock skew scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Swarup Bhunia , Nilanjan Banerjee , Qikai Chen , Hamid Mahmoodi-Meimand , Kaushik Roy A novel synthesis approach for active leakage power reduction using dynamic supply gating. [Citation Graph (0, 0)][DBLP ] Conf ] Kundan Nepal , R. Iris Bahar , Joseph L. Mundy , William R. Patterson , Alexander Zaslavsky Designing logic circuits for probabilistic computation in the presence of noise. [Citation Graph (0, 0)][DBLP ] Conf ] Peggy B. McGee , Steven M. Nowick A lattice-based framework for the classification and design of asynchronous pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] King Ho Tam , Lei He Power optimal dual-Vdd buffered tree considering buffer stations and blockages. [Citation Graph (0, 0)][DBLP ] Conf ] Brent Goplen , Prashant Saxena , Sachin S. Sapatnekar Net weighting to reduce repeater counts during placement. [Citation Graph (0, 0)][DBLP ] Conf ] Cliff C. N. Sze , Charles J. Alpert , Jiang Hu , Weiping Shi Path based buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Haoxing Ren , David Zhigang Pan , Charles J. Alpert , Paul Villarrubia Diffusion-based placement migration. [Citation Graph (0, 0)][DBLP ] Conf ] Francine Bacchini , Gabe Moretti , Harry Foster , Janick Bergeron , Masayuki Nakamura , Shrenik Mehta , Laurent Ducousso Is methodology the highway out of verification hell? [Citation Graph (0, 0)][DBLP ] Conf ] Hongliang Chang , Sachin S. Sapatnekar Full-chip analysis of leakage power under process variations, including spatial correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Navid Azizi , Muhammad M. Khellah , Vivek De , Farid N. Najm Variations-aware low-power design with voltage scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Srivastava , Saumil Shah , Kanak Agarwal , Dennis Sylvester , David Blaauw , Stephen W. Director Accurate and efficient gate-level parametric yield estimation considering correlated variations in leakage power and performance. [Citation Graph (0, 0)][DBLP ] Conf ] Sarvesh Bhardwaj , Sarma B. K. Vrudhula Leakage minimization of nano-scale circuits in the presence of systematic and random variations. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Urard , L. Paumier , P. Georgelin , T. Michel , V. Lebars , E. Yeo , B. Gupta A 135Mbps DVB-S2 compliant codec based on 64800-bit LDPC and BCH codes (ISSCC paper 24.3). [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Royannez , Hugh Mair , Franck Dahan , Mike Wagner , Mark Streeter , Laurent Bouetel , Joel Blasquez , H. Clasen , G. Semino , Julie Dong , D. Scott , B. Pitts , Claudine Raibaut , Uming Ko A design platform for 90-nm leakage reduction techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Arun Natarajan , Abbas Komijani , Ali Hajimiri A 24 GHz phased-array transmitter in 0.18µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Taeweon Suh , Daehyun Kim , Hsien-Hsin S. Lee Cache coherence support for non-shared bus architecture on heterogeneous MPSoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Jongman Kim , Dongkook Park , Theo Theocharides , Narayanan Vijaykrishnan , Chita R. Das A low latency router supporting adaptivity for on-chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Sudeep Pasricha , Nikil D. Dutt , Elaheh Bozorgzadeh , Mohamed Ben-Romdhane Floorplan-aware automated synthesis of bus-based communication architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna Sekar , Kanishka Lahiri , Anand Raghunathan , Sujit Dey FLEXBUS: a high-performance system-on-chip communication architecture with a dynamically configurable topology. [Citation Graph (0, 0)][DBLP ] Conf ] Sven Heithecker , Rolf Ernst Traffic shaping for an FPGA based SDRAM controller with complex QoS requirements. [Citation Graph (0, 0)][DBLP ] Conf ] Vidyasagar Nookala , Ying Chen , David J. Lilja , Sachin S. Sapatnekar Microarchitecture-aware floorplanning using a statistical design of experiments approach. [Citation Graph (0, 0)][DBLP ] Conf ] Zhong Xiu , Rob A. Rutenbar Timing-driven placement by grid-warping. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Brenner , Markus Struzyna Faster and better global placement by a new transportation algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tsung-Yi Ho , Chen-Feng Chang , Yao-Wen Chang , Sao-Jie Chen Multilevel full-chip routing for the X-based architecture. [Citation Graph (0, 0)][DBLP ] Conf ] David P. Magee Matlab extensions for the development, testing and verification of real-time DSP software. [Citation Graph (0, 0)][DBLP ] Conf ] Tejas M. Bhatt , Dennis McCain Matlab as a development environment for FPGA design. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Fox , Lou Covey , Susan Mack , David Heacock , Ed P. Huijbregts , Vess Johnson , Avner Kornfeld , Andrew Yang , Paul S. Zuchowski Should our power approach be current? [Citation Graph (0, 0)][DBLP ] Conf ] Ali Iranli , Massoud Pedram DTM: dynamic tone mapping for backlight scaling. [Citation Graph (0, 0)][DBLP ] Conf ] Dexin Li , Pai H. Chou Application/architecture power co-optimization for embedded systems powered by renewable sources. [Citation Graph (0, 0)][DBLP ] Conf ] Le Yan , Lin Zhong , Niraj K. Jha User-perceived latency driven voltage scaling for interactive applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jianli Zhuo , Chaitali Chakrabarti System-level energy-efficient dynamic task scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Xu , Kan-Lin Hsiung , Xin Li , Ivan Nausieda , Stephen P. Boyd , Lawrence T. Pileggi OPERA: optimization with ellipsoidal uncertainty for robust analog IC design. [Citation Graph (0, 0)][DBLP ] Conf ] Jihong Ren , Mark R. Greenstreet A unified optimization framework for equalization filter synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Sambuddha Bhattacharya , Nuttorn Jangkrajarng , C.-J. Richard Shi Template-driven parasitic-aware optimization of analog integrated circuit layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Nieuwoudt , Yehia Massoud Multi-level approach for integrated spiral inductor optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Chirayu S. Amin , Noel Menezes , Kip Killpack , Florentin Dartu , Umakanta Choudhury , Nagib Hakim , Yehea I. Ismail Statistical static timing analysis: how simple can we get? [Citation Graph (0, 0)][DBLP ] Conf ] Yu Cao , Lawrence T. Clark Mapping statistical process variations toward circuit performance variability: an analytical modeling approach. [Citation Graph (0, 0)][DBLP ] Conf ] Peng Li Power grid simulation via efficient sampling-based sensitivity analysis and hierarchical symbolic relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Yaron Wolfsthal , Rebecca M. Gott Formal verification: is it real enough? [Citation Graph (0, 0)][DBLP ] Conf ] Umberto Rossi Can we really do without the support of formal methods in the verification of large designs? [Citation Graph (0, 0)][DBLP ] Conf ] Prosenjit Chatterjee Streamline verification process with formal property verification to meet highly compressed design cycle. [Citation Graph (0, 0)][DBLP ] Conf ] Seraj Ahmad , Rabi N. Mahapatra TCAM enabled on-chip logic minimization. [Citation Graph (0, 0)][DBLP ] Conf ] Sergiu Nedevschi , Rabin K. Patra , Eric A. Brewer Hardware speech recognition for user interfaces in low cost, low power devices. [Citation Graph (0, 0)][DBLP ] Conf ] Guangyu Chen , Mahmut T. Kandemir Improving java virtual machine reliability for memory-constrained embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Corey Goldfeder Frequency-based code placement for embedded multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Joel Coburn , Srivaths Ravi , Anand Raghunathan Power emulation: a new paradigm for power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] John Wei , Chris Rowen Implementing low-power configurable processors: practical options and tradeoffs. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Luo , Jia Yu , Jun Yang , Laxmi N. Bhuyan Low power network processor design using clock gating. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Jayakumar , Sunil P. Khatri A variation tolerant subthreshold design approach. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Lin , Lei He Leakage efficient chip-level dual-Vdd assignment with time slack allocation for FPGA power reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Marvin Tom , Guy G. Lemieux Logic block clustering of large designs for channel-width constrained FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Carlos Schneider Beck , Luigi Carro Dynamic reconfiguration with binary translation: breaking the ILP barrier with software compatibility. [Citation Graph (0, 0)][DBLP ] Conf ] Malay K. Ganai , Aarti Gupta , Pranav Ashar Beyond safety: customized SAT-based model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Domagoj Babic , Jesse D. Bingham , Alan J. Hu Efficient SAT solving: beyond supercubes. [Citation Graph (0, 0)][DBLP ] Conf ] HoonSang Jin , Fabio Somenzi Prime clauses for fast enumeration of satisfying assignments to boolean circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Zhang , Mukul R. Prasad , Michael S. Hsiao , Thomas Sidle Dynamic abstraction using SAT-based BMC. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Tom Bonifield , Abha Singh , Clive Bittlestone , Usha Narasimha , Viet Le , Anthony M. Hill BEOL variability and impact on RC extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Carlo Guardiani , Massimo Bertoletti , Nicola Dragone , Marco Malcotti , Patrick McNamara An effective DFM strategy requires accurate process and IP pre-characterization. [Citation Graph (0, 0)][DBLP ] Conf ] James Tschanz , Keith A. Bowman , Vivek De Variation-tolerant circuits: circuit solutions and techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Farid N. Najm On the need for statistical timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] David Blaauw , Kaviraj Chopra CAD tools for variation tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Matt Nowak , Riko Radojcic Are there economic benefits in DFM? [Citation Graph (0, 0)][DBLP ] Conf ] Allon Adir , Hezi Azatchi , Eyal Bin , Ofer Peled , Kirill Shoikhet A generic micro-architectural test plan approach for microprocessor verification. [Citation Graph (0, 0)][DBLP ] Conf ] Sudheendra Hangal , Naveen Chandra , Sridhar Narayanan , Sandeep Chakravorty IODINE: a tool to automatically infer dynamic invariants for hardware designs. [Citation Graph (0, 0)][DBLP ] Conf ] Allon Adir , Yaron Arbetman , Bella Dubrov , Yossi Lichtenstein , Michal Rimon , Michael Vinov , Massimo A. Calligaro , Andrew Cofler , Gabriel Duffy VLIW: a case study of parallelism verification. [Citation Graph (0, 0)][DBLP ] Conf ] Ilya Wagner , Valeria Bertacco , Todd M. Austin StressTest: an automatic approach to test generation via activity monitors. [Citation Graph (0, 0)][DBLP ] Conf ] Sadik Ezer , Scott Johnson Smart diagnostics for configurable processor verification. [Citation Graph (0, 0)][DBLP ] Conf ] Yongseok Cheon , Pei-Hsin Ho , Andrew B. Kahng , Sherief Reda , Qinke Wang Power-aware placement. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Chowdhary , Karthik Rajagopal , Satish Venkatesan , Tung Cao , Vladimir Tiourin , Yegna Parasuram , Bill Halpin How accurately can we model timing in a placement engine? [Citation Graph (0, 0)][DBLP ] Conf ] Hiran Tennakoon , Carl Sechen Efficient and accurate gate sizing with piecewise convex delay models. [Citation Graph (0, 0)][DBLP ] Conf ] Yuantao Peng , Xun Liu Freeze: engineering a fast repeater insertion solver for power minimization using the ellipsoid method. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Geilen , Twan Basten , Sander Stuijk Minimising buffer requirements of synchronous dataflow graphs with model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Fei Su , Krishnendu Chakrabarty Unified high-level synthesis and module placement for defect-tolerant microfluidic biochips. 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