Conferences in DBLP
Thomas Pennino Customers, Vendors, and Universities: Determining the Future of EDA Together (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Michael Kishinevsky , Jordi Cortadella , Alex Kondratyev Asynchronous Interface Specification, Analysis and Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Roberto Passerone , James A. Rowson , Alberto L. Sangiovanni-Vincentelli Automatic Synthesis of Interfaces Between Incompatible Protocols. [Citation Graph (0, 0)][DBLP ] Conf ] James Smith , Giovanni De Micheli Automated Composition of Hardware Components. [Citation Graph (0, 0)][DBLP ] Conf ] Mike Chou , Jacob White Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC's. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Demir , Amit Mehrotra , Jaijeet S. Roychowdhury Phase Noise in Oscillators: A Unifying Theory and Numerical Methods for Characterisation. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Carro , Marcelo Negreiros Efficient Analog Test Methodology Based on Adaptive Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Bogdan G. Arsintescu , Edoardo Charbon , Enrico Malavasi , Umakanta Choudhury , William H. Kao General AC Constraint Transformation for Analog ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Jacob Rael , Ahmadreza Rofougaran , Asad A. Abidi Design Methodology Used in a Single-Chip CMOS 900 MHz Spread-Spectrum Wireless Transceiver. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Hilgenstock , Klaus Herrmann , Jan Otterstedt , Dirk Niggemeyer , Peter Pirsch A Video Signal Processor for MIMD Multiprocessing. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Peter Wittenburg , Willm Hinrichs , Johannes Kneip , Martin Ohmacht , Mladen Berekovic , Hanno Lieske , Helge Kloos , Peter Pirsch Realization of a Programmable Parallel DSP for High Performance Image Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Roy A. Sutton , Vason P. Srini , Jan M. Rabaey A Multiprocessor DSP System Using PADDI-2. [Citation Graph (0, 0)][DBLP ] Conf ] A. Grbic , Stephen Dean Brown , S. Caranci , R. Grindley , M. Gusat , Guy G. Lemieux , K. Loveless , Naraig Manjikian , Sinisa Srbljic , Michael Stumm , Zvonko G. Vranesic , Zeljko Zilic Design and Implementation of the NUMAchine Multiprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] James Shin Young , Josh MacDonald , Michael Shilman , Abdallah Tabbara , Paul N. Hilfinger , A. Richard Newton Design and Specification of Embedded Systems in Java Using Successive, Formal Refinement. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Leao da Silva Jr. , Chantal Ykman-Couvreur , Miguel Miranda , Kris Croes , Sven Wuytack , Gjalt G. de Jong , Francky Catthoor , Diederik Verkest , Paul Six , Hugo De Man Efficient System Exploration and Synthesis of Applications with Dynamic Data Storage and Intensive Data Transfer. [Citation Graph (0, 0)][DBLP ] Conf ] Ireneusz Karkowski , Henk Corporaal Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Gaetano Borriello Modal Processes: Towards Enhanced Retargetability Through Control Composition of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth L. Shepard Design Methodologies for Noise in Digital Integrated Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Kenneth L. Shepard , Takahide Inone Taming Noise in Deep Submicron Digital Integrated Circuits (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Lakshminarayana , Niraj K. Jha FACT : A Framework for the Application of Throughput and Power Optimizing Transformations to Control-Flow Intensive Behavioral Descriptions.Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Lakshminarayana , Anand Raghunathan , Niraj K. Jha Incorporating Speculative Execution into Scheduling of Control-Flow Intensive Behavioral Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Shantanu Tarafdar , Miriam Leeser The DT-Model: High-Level Synthesis Using Data Transfers. [Citation Graph (0, 0)][DBLP ] Conf ] Moonwook Oh , Soonhoi Ha Rate Optimal VLSI Design from Data Flow Graph. [Citation Graph (0, 0)][DBLP ] Conf ] Ralph H. J. M. Otten , Robert K. Brayton Planning for Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Amir H. Salek , Jinan Lou , Massoud Pedram A DSM Design Flow: Putting Floorplanning, Technology-Napping, and Gate-Placement Together. [Citation Graph (0, 0)][DBLP ] Conf ] Peter R. Sutton , Stephen W. Director Framework Encapsulations: A New Approach to CAD Tool Interoperability. [Citation Graph (0, 0)][DBLP ] Conf ] Ken Hines , Gaetano Borriello A Geographically Distributed Framework for Embedded System Design and Validation. [Citation Graph (0, 0)][DBLP ] Conf ] Francis L. Chan , Mark D. Spiller , A. Richard Newton WELD - An Environment for Web-based Electronic Design. [Citation Graph (0, 0)][DBLP ] Conf ] Farzan Fallah , Srinivas Devadas , Kurt Keutzer OCCOM: Efficient Computation of Observability-Based Code Coverage Metrics for Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Raanan Grinwald , Eran Harel , Michael Orgad , Shmuel Ur , Avi Ziv User Defined Coverage - A Tool Supported Methodology for Design Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Joshua Marantz Enhanced Visibility and Performance in Functional Verification by Reconstruction. [Citation Graph (0, 0)][DBLP ] Conf ] Namseung Kim , Hoon Choi , Seungjong Lee , Seungwang Lee , In-Cheol Park , Chong-Min Kyung Virtual Chip: Making Functional Models Work on Real Target Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Heller Hardware/Software Co-Design: The Next Embedded System Design Challenge (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Inki Hong , Darko Kirovski , Gang Qu , Miodrag Potkonjak , Mani B. Srivastava Power Optimization of Variable Voltage Core-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Giuseppe A. Paleologo , Luca Benini , Alessandro Bogliolo , Giovanni De Micheli Policy Optimization for Dynamic Power Management. [Citation Graph (0, 0)][DBLP ] Conf ] Yanbing Li , Jörg Henkel A Framework for Estimation and Minimizing Energy Dissipation of Embedded HW/SW Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peixin Zhong , Pranav Ashar , Sharad Malik , Margaret Martonosi Using Reconfigurable Computing Techniques to Accelerate Problems in the CAD Domain: A Case Study with Boolean Satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Nicole Drechsler , Wolfgang Günther Fast Exact Minimization of BDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Hinsberger , Reiner Kolla Boolean Matching for Large Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Weiping Shi , Jianguo Liu , Naveen Kakani , Tiejun Yu A Fast Hierarchical Algorithm for 3-D Capacitance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] E. Aykut Dengi , Ronald A. Rohrer Boundary Element Method Macromodels for 2-D Hierachical Capacitance Extraction. [Citation Graph (0, 0)][DBLP ] Conf ] Jinsong Zhao , Wayne Wei-Ming Dai , Sharad Kapur , David E. Long Efficient Three-Dimensional Extraction Based on Static and Full-Wave Layered Green's Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Nevine Nassif , Madhav P. Desai , Dale H. Hall Robust Elmore Delay Models Suitable for Full Chip Timing Verification of a 600MHz CMOS Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Robert M. McGraw , James H. Aylor , Robert H. Klenke A Top-Down Design Environment for Developing Pipelined Datapaths. [Citation Graph (0, 0)][DBLP ] Conf ] Rita Yu Chen , Robert Michael Owens , Mary Jane Irwin , Raminder Singh Bajwa Validation of an Architectural Level Power Analysis Technique. [Citation Graph (0, 0)][DBLP ] Conf ] Toshihiro Hattori , Yusuke Nitta , Mitsuho Seki , Susumu Narita , Kunio Uchiyama , Tsuyoshi Takahashi , Ryuichi Satomura Design Methodology of a 200MHz Superscalar Microprocessor: SH-4. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Ohr How Much Analog Does a Designer Need to Know for Successful Mixed-Signal Design? (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo de Veciana , Margarida F. Jacome , J.-H. Guo Hierarchical Algorithms for Assessing Probabilistic Constraints on System Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Asawaree Kalavade , Pratyush Moghé A Tool for Performance Estimation of Networked Embedded End-systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Dasdan , Dinesh Ramanathan , Rajesh K. Gupta Rate Derivation and Its Applications to Reactive, Real-Time Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Eisenmann , Frank M. Johannes Generic Global Placement and Floorplanning. [Citation Graph (0, 0)][DBLP ] Conf ] Phiroze N. Parakh , Richard B. Brown , Karem A. Sakallah Congestion Driven Quadratic Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Maogang Wang , Prithviraj Banerjee , Majid Sarrafzadeh Potential-NRG: Placement with Incomplete Data. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Jong Fang , Allen C.-H. Wu Performance-Driven Multi-FPGA Partitioning Using Functional Clustering and Replication. [Citation Graph (0, 0)][DBLP ] Conf ] Jaewon Oh , Massoud Pedram Multi-Pad Power/Ground Network Design for Uniform Distribution of Ground Bounce. [Citation Graph (0, 0)][DBLP ] Conf ] Tong Li , Sung-Mo Kang Layout Extraction and Verification Methodology CMOS I/O Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nuno Alexandre Marques , Mattan Kamon , Jacob White , Luis Miguel Silveira A Mixed Nodal-Mesh Formulation for Efficient Extraction and Passive Reduced-Order Modeling of 3D Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Byron Krauter , Sharad Mehrotra Layout Based Frequency Dependent Inductance and Resistance Extraction for On-Chip Interconnect Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Lisa Guerra , Miodrag Potkonjak , Jan M. Rabaey A Methodology for Guided Behavioral-Level Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Schaumont , Serge Vernalde , Luc Rijnders , Marc Engels , Ivo Bolsens A Programming Environment for the Design of Complex High Speed ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Chunho Lee , Johnson Kin , Miodrag Potkonjak , William H. Mangione-Smith Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Randal E. Bryant , Gerry Musgrave User Experience with High Level Formal Verification (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] David L. Dill What's Between Simulation and Formal Verification? (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Chang Wu Optimal FPGA Mapping and Retiming with Efficient Initial State Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Victor N. Kravets , Karem A. Sakallah M32: A Constructive multilevel Logic Synthesis System. [Citation Graph (0, 0)][DBLP ] Conf ] Shih-Chieh Chang , David Ihsin Cheng Efficient Boolean Division and Substitution. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Kukimoto , Robert K. Brayton , Prashant Sawkar Delay-Optimal Technology Mapping by DAG Covering. [Citation Graph (0, 0)][DBLP ] Conf ] David S. Kung A Fast Fanout Optimization Algorithm for Near-Continuous Buffer Libraries. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Patrick H. Madden Performance Driven Multi-Layer General Area Routing for PCB/MCM Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Charles J. Alpert , Anirudh Devgan , Stephen T. Quay Buffer Insertion for Noise and Delay Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] John Lillis , Premal Buch Table-Lookup Methods for Improved Performance-Driven Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Hai Zhou , D. F. Wong Global Routing with Crosstalk Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Hsiao-Ping Tseng , Louis Scheffer , Carl Sechen Timing and Crosstalk Driven Area Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Arun N. Lokanathan , Jay B. Brockman Process Multi-Circuit Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Rajendran Panda , Abhijit Dharchoudhury , Tim Edwards , Joe Norton , David Blaauw Migration: A New Technique to Improve Synthesized Designs Through Incremental Customization. [Citation Graph (0, 0)][DBLP ] Conf ] Julian Culetu , Chaim Amir , John MacDonald A Practical Repeater Insertion Method in High Speed VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Paolo Ienne , Alexander Grießing Practical Experiences with Standard-Cell Based Datapath Design Tools: Do We Really Need Regular Layouts? [Citation Graph (0, 0)][DBLP ] Conf ] Michael Orshansky , James C. Chen , Chenming Hu A Statistical Performance Simulation Methodology for VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Behzad Razavi RF IC Design Challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Al Dunlop , Alper Demir , Peter Feldmann , Sharad Kapur , David E. Long , Robert C. Melville , Jaijeet S. Roychowdhury Tools and Methodology for RF IC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Y. Yuan Electromagnetic Modeling and Signal Integrity Simulation of Power/Ground Networks in High Speed Digital Packages and Printed Circuit Boards. [Citation Graph (0, 0)][DBLP ] Conf ] Darko Kirovski , Miodrag Potkonjak Efficient Coloring of a Large Spectrum of Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Taewhan Kim , William Jao , Steven W. K. Tjiang Arithmetic Optimization Using Carry-Save-Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Ganesh Lakshminarayana , Niraj K. Jha Synthesis of Power-Optimized and Area-Optimized Circuits from Hierarchical Behavioral Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Kavita Ravi , Kenneth L. McMillan , Thomas R. Shiple , Fabio Somenzi Approximation and Decomposition of Binary Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar G. Govindaraju , David L. Dill , Alan J. Hu , Mark Horowitz Approximate Reachability with BDDs Using Overlapping Projections. [Citation Graph (0, 0)][DBLP ] Conf ] Abelardo Pardo , Gary D. Hachtel Incremental CTL Model Checking Using BDD Subsetting. [Citation Graph (0, 0)][DBLP ] Conf ] Rony Kay , Lawrence T. Pileggi PRIMO: Probability Interpretation of Moments for Delay Calculation. [Citation Graph (0, 0)][DBLP ] Conf ] Ying Liu , Lawrence T. Pileggi , Andrzej J. Strojwas ftd : An Exact Frequency to Time Domain Conversion for Reduced Order RLC Interconnect Models.Citation Graph (0, 0)][DBLP ] Conf ] Fang-Jou Liu , Chung-Kuan Cheng Extending Moment Computation to 2-Port Circuit Representations. [Citation Graph (0, 0)][DBLP ] Conf ] Tuyen V. Nguyen , Anirudh Devgan , Ognen J. Nastov Adjoint Transient Sensitivity Computation in Piecewise Linear Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Kimiyoshi Usami , Mutsunori Igarashi , Takashi Ishikawa , Masahiro Kanazawa , Masafumi Takahashi , Mototsugu Hamada , Hideho Arakida , Toshihiro Terazawa , Tadahiro Kuroda Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Liqiong Wei , Zhanping Chen , Mark Johnson , Kaushik Roy , Vivek De Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] James Kao , Siva Narendra , Anantha Chandrakasan MTCMOS Hierarchical Sizing Based on Mutual Exclusive Discharge Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] A. Richard Newton Technical Challenges of IP and System-on-Chip: The ASIC Vendor Perspective (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Bill Lin Software Synthesis of Process-Based Concurrent Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Youpyo Hong , Peter A. Beerel , Luciano Lavagno , Ellen Sentovich Don't Care-Based BDD Minimization for Embedded Software. [Citation Graph (0, 0)][DBLP ] Conf ] Silvina Hanono , Srinivas Devadas Instruction Selection, Resource Allocation, and Scheduling in the AVIV Retargetable Code Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Haris Lekatsas , Wayne Wolf Code Compression for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Clark W. Barrett , David L. Dill , Jeremy R. Levitt A Decision Procedure for Bit-Vector Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Farzan Fallah , Srinivas Devadas , Kurt Keutzer Functional Vector Generation for HDL Models Using Linear Programming and 3-Satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Li-C. Wang , Magdy S. Abadir , Nari Krishnamurthy Automatic Generation of Assertions for Formal Verification of PowerPC Microprocessor Arrays Using Symbolic Trajectory Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Aagaard , Robert B. Jones , Carl-Johan H. Seger Combining Theorem Proving and Trajectory Evaluation in an Industrial Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Sujit Dey , Niraj K. Jha A Fast and Low Cost Testing Technique for Core-Based System-on-Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Ishwar Parulkar , Sandeep K. Gupta , Melvin A. Breuer Introducing Redundant Computations in a Behavior for Reducing BIST Resources. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Niraj K. Jha , Sudipta Bhawmik A BIST Scheme for RTL Controller-Data Paths Based on Symbolic Testability Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Yehea I. Ismail , Eby G. Friedman , José Luis Neves Figures of Merit to Characterize the Importance of On-Chip Inductance. [Citation Graph (0, 0)][DBLP ] Conf ] Yehia Massoud , Steve S. Majors , Tareq Bustami , Jacob White Layout Techniques for Minimizing On-Chip Interconnect Self Inductance. [Citation Graph (0, 0)][DBLP ] Conf ] N. S. Nagaraj , Frank Cano , Haldun Haznedar , Duane Young A Practical Approach to Static Signal Electromigration Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Dangelo Design Productivity: How To Measure It, How To Improve It (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Kukimoto , Robert K. Brayton Hierarchical Functional Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Tod Amon , Gaetano Borriello , Jiwen Liu Making Complex Timing Relationships Readable: Presburger Formula Simplicication Using Don't Cares. [Citation Graph (0, 0)][DBLP ] Conf ] Mahadevamurty Nemani , Farid N. Najm Delay Estimation VLSI Circuits from a High-Level View. [Citation Graph (0, 0)][DBLP ] Conf ] Florentin Dartu , Lawrence T. Pileggi TETA: Transistor-Level Engine for Timing Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] C. Han Yang , David L. Dill Validation with Guided Search of the State Space. [Citation Graph (0, 0)][DBLP ] Conf ] Aiguo Xie , Peter A. Beerel Efficient State Classification of Finite State Markov Chains. [Citation Graph (0, 0)][DBLP ] Conf ] Gagan Hasteer , Anmol Mathur , Prithviraj Banerjee An Implicit Algorithm for Finding Steady States and its Application to FSM Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Adnan Aziz , James H. Kukula , Thomas R. Shiple Hybrid Verification Using Saturated Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Dechang Sun , Bapiraju Vinnakota , Wanli Jiang Fast State Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Aiman H. El-Maleh , Mark Kassab , Janusz Rajski A Fast Sequential Learning Technique for Real Circuits with Application to Enhancing ATPG Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen , Juin-Yeu Joseph Lu Fault-Simulation Based Design Error Diagnosis for Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Scott A. Taylor , Michael Quinn , Darren Brown , Nathan Dohm , Scot Hildebrandt , James Huggins , Carl Ramey Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor - The DEC Alpha 21264 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Yossi Malka , Avi Ziv Design Reliability - Estimation through Statistical Analysis of Bug Discovery Data. [Citation Graph (0, 0)][DBLP ] Conf ] Adrian Evans , Allan Silburt , Gary Vrckovnik , Thane Brown , Mario Dufresne , Geoffrey Hall , Tung Ho , Ying Liu Functional Verification of Large ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Erach Desai The EDA Start-up Experience: The First Product (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Kunle Olukotun , Mark Heinrich , David Ofelt Digital System Simulation: Methodologies and Examples. [Citation Graph (0, 0)][DBLP ] Conf ] Yufeng Luo , Tjahjadi Wongsonegoro , Adnan Aziz Hybrid Techniques for Fast Functional Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry Bauer , Michael Bershteyn , Ian Kaplan , Paul Vyedin A Reconfigurable Logic Machine for Fast Event-Driven Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Kim , Prithviraj Banerjee Parallel Algorithms for Power Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Zhanping Chen , Kaushik Roy A Power Macromodeling Technique Based on Power Sensitivity. [Citation Graph (0, 0)][DBLP ] Conf ] Qinru Qiu , Qing Wu , Massoud Pedram Maximum Power Estimation Using the Limiting Distributions of Extreme Order Statistics. [Citation Graph (0, 0)][DBLP ] Conf ] Byunggyu Kwak , Eun Sei Park An Optimization-Based Error Calculation for Statistical Power Estimation of CMOS Logic Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Masahiro Fujita , Arlindo L. Oliveira Using Complementation and Resequencing to Minimize Transitions. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Helge Anderson , Stephen Dean Brown Technology Mapping for Large Complex PLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Songjie Xu Delay-Optimal Technology Mapping for FPGAs with Heterogeneous LUTs. [Citation Graph (0, 0)][DBLP ] Conf ] Madhukar R. Korupolu , K. K. Lee , D. F. Wong Exact Tree-based FPGA Technology Mapping for Logic Blocks with Independent LUTs. [Citation Graph (0, 0)][DBLP ] Conf ] Jie-Hong Roland Jiang , Jing-Yang Jou , Juinn-Dar Huang Compatible Class Encoding in Hyper-Function Decomposition for FPGA Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Balakrishna Kumthekar , Luca Benini , Enrico Macii , Fabio Somenzi In-Place Power Optimization for LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jan-Min Hwang , Feng-Yi Chiang , TingTing Hwang A Re-engineering Approach to Low Power FPGA Design Using SPFD. [Citation Graph (0, 0)][DBLP ] Conf ] Michael K. Gowan , Larry L. Biro , Daniel B. Jackson Power Considerations in the Design of the Alpha 21264 Microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Tiwari , Deo Singh , Suresh Rajgopal , Gaurav Mehta , Rakesh Patel , Franklin Baez Reducing Power in High-Performance Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Abhijit Dharchoudhury , Rajendran Panda , David Blaauw , Ravi Vaidyanathan , Bogdan Tutuianu , David Bearden Design and Analysis of Power Distribution Networks in PowerPC Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory Steele , David Overhauser , Steffen Rochel , Syed Zakir Hussain Full-Chip Verification Methods for DSM Power Distribution Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Prab Varma System Chip Test Challenges, Are There Solutions Today? (Panel). [Citation Graph (0, 0)][DBLP ] Conf ] Yervant Zorian System-Chip Test Strategies (Tutorial). [Citation Graph (0, 0)][DBLP ] Conf ] José C. Monteiro , Arlindo L. Oliveira Finite State Machine Decomposition For Low Power. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Giovanni De Micheli , Antonio Lioy , Enrico Macii , Giuseppe Odasso , Massimo Poncino Computational Kernels and their Application to Sequential Power Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Seawright , Wolfgang Meyer Partitioning and Optimizing Controllers Synthesized from Hierarchical High-Level Descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , John Lach , William H. Mangione-Smith , Stefanus Mantik , Igor L. Markov , Miodrag Potkonjak , Paul Tucker , Huijuan Wang , Gregory Wolfe Watermarking Techniques for Intellectual Property Protection. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Stefanus Mantik , Igor L. Markov , Miodrag Potkonjak , Paul Tucker , Huijuan Wang , Gregory Wolfe Robust IP Watermarking Methodologies for Physical Design. [Citation Graph (0, 0)][DBLP ] Conf ] Scott Hauck , Stephen Knol Data Security for Web-based CAD. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Holtmann , Peter Blinzer Design of a SPDIF Receiver Using Protocol Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Hyuk Yang , Byoung-Woon Kim , Sang-Jun Nam , Jang-Ho Cho , Sung-Won Seo , Chang-Ho Ryu , Young-Su Kwon , Dae-Hyun Lee , Jong-Yeol Lee , Jong-Sun Kim , Hyun-Dhong Yoon , Jae-Yeol Kim , Kun-Moo Lee , Chan-Soo Hwang , In-Hyung Kim , Jun Sung Kim , Kwang-Il Park , Kyu Ho Park , Yong-Hoon Lee , Seung Ho Hwang , In-Cheol Park , Chong-Min Kyung MetaCore: An Application Specific DSP Development System. [Citation Graph (0, 0)][DBLP ] Conf ] Tullio Cuatto , Claudio Passerone , Luciano Lavagno , Attila Jurecska , Antonino Damiano , Claudio Sansoè , Alberto L. Sangiovanni-Vincentelli A Case Study in Embedded System Design: An Engine Control Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas W. Albrecht , Johann Notbauer , Stefan Rohringer HW/SW CoVerification Performance Estimation and Benchmark for a 24 Embedded RISC Core Design. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gajski , Frank Vahid , Sanjiv Narayan , Jie Gong System-level exploration with SpecSyn. [Citation Graph (0, 0)][DBLP ] Conf ] 