|
|
Conferences in DBLP
- Rainer Leupers
Code Selection for Media Processors with SIMD Instructions. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:4-8 [Conf]
- Sumit Gupta, Rajesh K. Gupta, Miguel Miranda, Francky Catthoor
Analysis of High-Level Address Code Transformations for Programmable Processors. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:9-13 [Conf]
- Chunghee Kim, Luciano Lavagno, Alberto L. Sangiovanni-Vincentelli
Free MDD-Based Software Optimization Techniques for Embedded Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:14-0 [Conf]
- Yung-Hsiang Lu, Eui-Young Chung, Tajana Simunic, Giovanni De Micheli, Luca Benini
Quantitative Comparison of Power Management Algorithms. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:20-26 [Conf]
- Marcello Lajolo, Anand Raghunathan, Sujit Dey, Luciano Lavagno
Efficient Power Co-Estimation Techniques for System-on-Chip Design. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:27-34 [Conf]
- Luca Benini, Giuliano Castelli, Alberto Macii, Enrico Macii, Massimo Poncino, Riccardo Scarsi
A Discrete-Time Battery Model for High-Level Power Estimation. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:35-0 [Conf]
- Robert Schwencker, Frank Schenkel, Helmut E. Graeb, Kurt Antreich
The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:42-47 [Conf]
- Oscar Guerra, E. Roca, Francisco V. Fernández, Ángel Rodríguez-Vázquez
A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:48-52 [Conf]
- Mohamed Dessouky, Marie-Minerve Louërat, Jacky Porte
Layout-Oriented Synthesis of High Performance Analog Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:53-57 [Conf]
- Sree Ganesan, Ranga Vemuri
Technology Mapping and Retargeting for Field-Programmable Analog Arrays. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:58-0 [Conf]
- Yervant Zorian, Michael Nicolaidis, Peter Muhmenthaler, David Y. Lepejian, Chris W. H. Strolenberg, Kees Veelenturf
Tutorial Statement. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:66- [Conf]
- Kees Veelenturf
The Road to Better Reliability and Yield Embedded DfM Tools. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:67- [Conf]
- Yervant Zorian
Yield Improvement and Repair Trade-Off for Large Embedded Memories. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:69-70 [Conf]
- Chris W. H. Strolenberg
Stay Away from Minimum Design-Rule Values. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:71-0 [Conf]
- Diederik Verkest, Joachim Kunkel, Frank Schirrmeister
System Level Design Using C++. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:74-0 [Conf]
- Roman L. Lysecky, Frank Vahid, Tony Givargis
Techniques for Reducing Read Latency of Core Bus Wrappers. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:84-91 [Conf]
- Frederik Vermeulen, Francky Catthoor, Hugo De Man, Diederik Verkest
Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:92-98 [Conf]
- Marcello Dalpasso, Alessandro Bogliolo, Luca Benini, Michele Favalli
Virtual Fault Simulation of Distributed IP-Based Designs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:99-0 [Conf]
- Xiaoping Tang, D. F. Wong, Ruiqi Tian
Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:106-111 [Conf]
- Youssef Saab
A New Effective And Efficient Multi-Level Partitioning Algorithm. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:112-116 [Conf]
- Ulrich Brenner, Jens Vygen
Faster Optimal Single-Row Placement with Fixed Ordering. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:117-121 [Conf]
- Youcef Bourai, C.-J. Richard Shi
Layout Compaction for Yield Optimization via Critical Area Minimization. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:122-0 [Conf]
- Sule Ozev, Ismet Bayraktaroglu, Alex Orailoglu
Test Synthesis for Mixed-Signal SOC Paths. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:128-133 [Conf]
- Makoto Sugihara, Hiroto Yasuura, Hiroshi Date
Analysis and Minimization of Test Time in a Combined BIST and External Test Approach. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:134-140 [Conf]
- Mounir Benabdenbi, Walid Maroufi, Meryem Marzouki
CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:141-145 [Conf]
- V. A. Zivkovic, Ronald J. W. T. Tangelder, Hans G. Kerkhoff
Design and Test Space Exploration of Transport-Triggered Architectures. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:146-0 [Conf]
- Axel Jantsch, Per Bjuréus
Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:154-160 [Conf]
- Per Bjuréus, Axel Jantsch
MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:161-168 [Conf]
- Mark B. Josephs, Dennis P. Furey
Delay-Insensitive Interface Specification and Synthesis. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:169-0 [Conf]
- F. Viglione, Guido Masera, Gianluca Piccinini, M. Ruo Roch, Maurizio Zamboni
A 50 Mbit/s Iterative Turbo-Decoder. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:176-180 [Conf]
- U. Girola, A. Picciriello, D. Vincenzoni
Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:181-185 [Conf]
- Takahiro Murooka, Toshiaki Miyazaki
Protocol Stack-Based Telecom-Emulator. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:186-0 [Conf]
- Wilm E. Donath, Prabhakar Kudva, Leon Stok, Paul Villarrubia, Lakshmi N. Reddy, Andrew Sullivan, Kanad Chakraborty
Transformational Placement and Synthesis. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:194-201 [Conf]
- Balakrishna Kumthekar, Fabio Somenzi
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:202-207 [Conf]
- Victor N. Kravets, Karem A. Sakallah
Constructive Library-Aware Synthesis Using Symmetries. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:208-0 [Conf]
- Jiun-Lang Huang, Chee-Kian Ong, Kwang-Ting Cheng
A BIST Scheme for On-Chip ADC and DAC Testing. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:216-220 [Conf]
- Yun-Che Wen, Kuen-Jong Lee
An on Chip ADC Test Structure. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:221-225 [Conf]
- Érika F. Cota, Michel Renovell, Florence Azaïs, Yves Bertrand, Luigi Carro, Marcelo Lubaszewski
Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:226-0 [Conf]
- Priyank Kalla, Zhihong Zeng, Maciej J. Ciesielski, ChiLai Huang
A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:232-236 [Conf]
- Praveen Yalagandula, Adnan Aziz, Vigyan Singhal
Automatic Lighthouse Generation for Directed State Space Search. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:237-242 [Conf]
- Jürgen Ruf, Thomas Kropf
Analyzing Real-Time Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:243-0 [Conf]
- Pierre Guerrier, Alain Greiner
A Generic Architecture for On-Chip Packet-Switched Interconnections. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:250-256 [Conf]
- Françoise Harmsze, Adwin H. Timmer, Jef L. van Meerbergen
Memory Arbitration and Cache Management in Stream-Based Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:257-262 [Conf]
- Massimo Baleani, Alberto Ferrari, Alberto L. Sangiovanni-Vincentelli, Claudio Turchetti
HW/SW Codesign of an Engine Management System. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:263-0 [Conf]
- Luca Macchiarulo, Shih-Ming Shu, Malgorzata Marek-Sadowska
Wave Steered FSMs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:270-276 [Conf]
- Jovanka Ciric, Gin Yee, Carl Sechen
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:277-282 [Conf]
- E. T. A. F. Jacobs, Michel R. C. M. Berkelaar
Gate Sizing Using a Statistical Delay Model. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:283-0 [Conf]
- Silvia Cataldo, Silvia Chiusano, Paolo Prinetto, Hans-Joachim Wunderlich
Optimal Hardware Pattern Generation for Functional BIST. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:292-297 [Conf]
- Irith Pomeranz, Sudhakar M. Reddy
Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:298-304 [Conf]
- Timothy J. Bergfeld, Dirk Niggemeyer, Elizabeth M. Rudnick
Diagnostic Testing of Embedded Memories Using BIST. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:305-0 [Conf]
- Luc Séméria, Koichi Sato, Giovanni De Micheli
Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:312-319 [Conf]
- Satish Ganesan, Ranga Vemuri
An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:320-325 [Conf]
- Oliver Bringmann, Wolfgang Rosenstiel, Carsten Menn
Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:326-332 [Conf]
- Jörg Henkel, Tony Givargis, Frank Vahid
Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:333-0 [Conf]
- Alper Demir, Peter Feldmann
Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:340-344 [Conf]
- Mark M. Gourary, Sergey G. Rusakov, Sergey L. Ulyanov, Michael M. Zharov, Kiran K. Gullapalli, Brian J. Mulvaney
A New Approach for Computation of Timing Jitter in Phase Locked Loops. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:345-349 [Conf]
- Piet Wambacq, Petr Dobrovolný, Stéphane Donnay, Marc Engels, Ivo Bolsens
Compact Modeling of Nonlinear Distortion in Analog Communication Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:350-0 [Conf]
- Vasco M. Manquinho, João P. Marques Silva
On Using Satisfiability-Based Pruning Techniques in Covering Algorithms. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:356-363 [Conf]
- Roberto Cordone, Fabrizio Ferrandi, Donatella Sciuto, Roberto Wolfler Calvo
An Efficient Heuristic Approach to Solve the Unate Covering Problem. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:364-371 [Conf]
- Christoph Scholl, Bernd Becker
On the Generation of Multiplexer Circuits for Pass Transistor Logic. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:372-0 [Conf]
- Joonyoung Kim, Jesse Whittemore, Karem A. Sakallah, João P. Marques Silva
On Applying Incremental Satisfiability to Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:380-384 [Conf]
- Fulvio Corno, Matteo Sonza Reorda, Giovanni Squillero, Alberto Manzone, Alessandro Pincetti
Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:385-389 [Conf]
- Alessandro Fin, Franco Fummi
A VHDL Error Simulator for Functional Test Generation. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:390-395 [Conf]
- Irith Pomeranz, Sudhakar M. Reddy
Functional Test Generation for Full Scan Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:396-0 [Conf]
- Praveen K. Murthy, Shuvra S. Bhattacharyya
Shared Memory Implementations of Synchronous Dataflow Specifications. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:404-410 [Conf]
- Marisa Luisa López-Vallejo, Jesús Grajal, Juan Carlos López
Constraint-Driven System Partitioning. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:411-416 [Conf]
- Nagaraj Shenoy, Prithviraj Banerjee, Alok N. Choudhary
A System-Level Synthesis Algorithm with Guaranteed Solution Quality. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:417-0 [Conf]
- Francky Catthoor, Nikil D. Dutt, Christoforos E. Kozyrakis
How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:426-0 [Conf]
- I-Min Liu, Adnan Aziz, D. F. Wong
Meeting Delay Constraints in DSM by Minimal Repeater Insertion. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:436-440 [Conf]
- Kei Hirose, Hiroto Yasuura
A Bus Delay Reduction Technique Considering Crosstalk. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:441-445 [Conf]
- Thorsten Adler, Erich Barke
Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:446-450 [Conf]
- Matthias Ringe, Thomas Lindenkreuz, Erich Barke
Static Timing Analysis Taking Crosstalk into Account. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:451-0 [Conf]
- Sungju Park, Taehyung Kim
A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:458-0 [Conf]
- Uros Kac, Franc Novak, Srecko Macek, Marina Santo Zarnik
Alternative Test Methods Using IEEE 1149.4. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:463-467 [Conf]
- Laurence Goodby, Alex Orailoglu
Test Quality and Fault Risk in Digital Filter Datapath BIST. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:468-475 [Conf]
- Richard Rosing
A Fault Simulation Methodology for MEMS. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:476-457 [Conf]
- George Logothetis, Klaus Schneider
Abstraction from Counters: An Application on Real-Time Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:486-493 [Conf]
- Felice Balarin
Automatic Abstraction for Worst-Case Analysis of Discrete Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:494-501 [Conf]
- Jae-Young Jang, In-Ho Moon, Gary D. Hachtel
Iterative Abstraction-Based CTL Model Checking. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:502-0 [Conf]
- Joseph Borel, Frank Ghenassia, Jean-Jacques Bronner, Irmtraud Rugen-Herzig, Wolfgang Rosenstiel, Anton Sauer
A Design Automation Roadmap for Europe Panel discussion. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:510-0 [Conf]
- Youxin Gao, D. F. Wong
Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:512-0 [Conf]
- Bernard N. Sheehan
Predicting Coupled Noise in RC Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:517-0 [Conf]
- Norman Chang, Shen Lin, O. Sam Nakagawa, Weize Xie, Lei He
Clocktree RLC Extraction with Efficient Inductance Modeling. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:522-0 [Conf]
- Chauchin Su, Yue-Tsang Chen, Mu-Jeng Huang, Gen-Nan Chen, Chung-Len Lee
All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:527-0 [Conf]
- Eduardo J. Peralías, Antonio J. Acosta, Adoración Rueda, José L. Huertas
A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:534-538 [Conf]
- Michael Scheffler, Gerhard Tröster
Assessing the Cost Effectiveness of Integrated Passives. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:539-543 [Conf]
- Luigi Carro, Adão Antônio de Souza Jr., Marcelo Negreiros, Gabriel Parmegiani Jahn, Denis Teixeira Franco
Non-Linear Components for Mixed Circuits Analog Front-End. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:544-0 [Conf]
- André Hergenhan, Wolfgang Rosenstiel
Static Timing Analysis of Embedded Software on Advanced Processor Architectures. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:552-559 [Conf]
- Iyad Ouaiss, Ranga Vemuri
Efficient Resource Arbitration in Reconfigurable Computing Environments. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:560-566 [Conf]
- Paul Pop, Petru Eles, Zebo Peng
Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:567-0 [Conf]
- Christopher K. Lennard, Patrick Schaumont, Gjalt G. de Jong, Anssi Haverinen, Pete Hardee
Standards for System-Level Design: Practical Reality or Solution in Search of a Question? [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:576-0 [Conf]
- Marcello Lajolo, Maurizio Rebaudengo, Matteo Sonza Reorda, Massimo Violante, Luciano Lavagno
Evaluating System Dependability in a Co-Design Framework. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:586-590 [Conf]
- Lorena Anghel, Michael Nicolaidis
Cost Reduction and Evaluation of a Temporary Faults Detecting Technique. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:591-598 [Conf]
- D. Weiler, O. Machul, D. Hammerschmidt, Bedrich J. Hosticka
Detection of Defective Sensor Elements Using Sigma-Delta-Modulation and a Matched Filter. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:599-0 [Conf]
- Dinesh Ramanathan, Rajesh K. Gupta
System Level Online Power Management Algorithms. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:606-605 [Conf]
- Cheng-Ta Hsieh, Massoud Pedram
Architectural Power Optimization by Bus Splitting. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:612-611 [Conf]
- Tohru Ishihara, Hiroto Yasuura
A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:617-616 [Conf]
- Michael Münch, Norbert Wehn, Bernd Wurth, Renu Mehra, Jim Sproch
Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:624-0 [Conf]
- Rolf Ernst, Grant Martin, Oz Levia, Pierre G. Paulin, Stamatis Vassiliadis, Kees A. Vissers
The Future of Flexible HW Platform Architectures Panel Discussion. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:634-0 [Conf]
- Sani R. Nassif
Designing Closer to the Edge. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:636-0 [Conf]
- José T. de Sousa, Vishwani D. Agrawal
Reducing the Complexity of Defect Level Modeling Using the Clustering Effect. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:640-644 [Conf]
- Juan M. Díez, Juan Carlos López
Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:645-649 [Conf]
- Khaled Saab, Naim Ben Hamida, Bozena Kaminska
Parametric Fault Simulation and Test Vector Generation. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:650-0 [Conf]
- Dragos Lungeanu, C.-J. Richard Shi
Parallel and Distributed VHDL Simulation. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:658-662 [Conf]
- Sungjoo Yoo, Jong-eun Lee, Jinyong Jung, Kyungseok Rha, Youngchul Cho, Kiyoung Choi
Fast Hardware-Software Coverification by Optimistic Execution of Real Processor. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:663-668 [Conf]
- Stefan Pees, Andreas Hoffmann, Heinrich Meyr
Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:669-673 [Conf]
- Peter M. Maurer
Logic Simulation Using Networks of State Machines. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:674-678 [Conf]
- Norbert Fröhlich, Volker Gloeckel, Josef Fleischmann
A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:679-0 [Conf]
- Carsten Rust, Friedhelm Stappert, Peter Altenbernd, Jürgen Tacken
From High-Level Specifications Down to Software Implementations of Parallel Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:686-691 [Conf]
- Martyn Edwards, Peter Green
An Object Oriented Design Method for Reconfigurable Computing Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:692-696 [Conf]
- Luigi Carro, Márcio Eduardo Kreutz, Flávio Rech Wagner, Márcio Oyamada
System Synthesis for Multiprocessor Embedded Applications. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:697-702 [Conf]
- Sérgio Akira Ito, Luigi Carro, Ricardo Pezzuol Jacobi
System Design Based on Single Language and Single-Chip Java ASIP Microcontroller. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:703-0 [Conf]
- Juin-Ming Lu, Cheng-Wen Wu
Cost and Benefit Models for Logic and Memory BIST. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:710-714 [Conf]
- Nicola Nicolici, Bashir M. Al-Hashimi
Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:715-722 [Conf]
- Joan Carletta, Christos A. Papachristou, Mehrdad Nourani
Detecting Undetectable Controller Faults Using Power Analysis. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:723-728 [Conf]
- Kabir Gulrajani, Michael S. Hsiao
Multi-Node Static Logic Implications for Redundancy Identification. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:729-0 [Conf]
- Tajana Simunic, Luca Benini, Peter W. Glynn, Giovanni De Micheli
Dynamic Power Management of Laptop Hard Disk. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:736- [Conf]
- Lars Kruse, Eike Schmidt, Gerd Jochens, Ansgar Stammermann, Wolfgang Nebel
Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:737- [Conf]
- Christian Paulus, Ulrich Kleine, Roland Thewes
Area Optimization of Analog Circuits Considering Matching Constraints. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:738- [Conf]
- F. M. Pérez-Montes, F. Medeiro, Rafael Domínguez-Castro, Francisco V. Fernández, Ángel Rodríguez-Vázquez
XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:739- [Conf]
- Ulf Pillkahn
Evaluation of Interconnects with TDR. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:740- [Conf]
- Peter Bach, Michael Bosch
Structural Testing on Real Boards. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:741- [Conf]
- Lovic Gauthier, Ahmed Amine Jerraya
Cycle-True Simulation of the ST10 Microcontroller. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:742- [Conf]
- Adam Morawiec, Raimund Ubar, Jaan Raik
Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:743- [Conf]
- José Machado da Silva, J. Soeiro Duarte, José Silva Matos
Mixed-Signal BIST Using Correlation and Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:744- [Conf]
- Karem A. Sakallah, Fadi A. Aloul, João P. Marques Silva
An Experimental Study of Satisfiability Search Heuristics. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:745- [Conf]
- Sunho Chang, Jong-Sun Kim, Lee-Sup Kim
A Memory Architecture with 4-Address Configurations for Video Signal Processing. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:746- [Conf]
- Gunter Haug, Udo Kebschull, Wolfgang Rosenstiel
A Hardware Platform for VLIW Based Emulation of Digital Designs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:747- [Conf]
- Ashok Halambi, Radu Cornea, Peter Grun, Nikil D. Dutt, Alexandru Nicolau
Architecture Exploration of Parameterizable EPIC SOC Architectures. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:748- [Conf]
- Sriram Govindarajan, Ranga Vemuri
Improving the Schedule Quality of Static-List Time-Constrained Scheduling. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:749- [Conf]
- Congguang Yang, Maciej J. Ciesielski
Synthesis for Mixed CMOS/PTl Logic. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:750- [Conf]
- Elena Dubrova, Peeter Ellervee, D. Michael Miller, Jon C. Muzio
TOP: An Algorithm for Three-Level Optimization of PLDs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:751- [Conf]
- Janusz Sosnowski, Tomasz Bech
Testing Arithmetic Coprocessor in System Environment. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:752- [Conf]
- José Manuel Moya, Francisco Moya, Juan Carlos López, Santiago Domínguez
A Flexible Specification Framework for Hardware-Software Codesign. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:753- [Conf]
- Jingyan Zuo, Stephen W. Director
An Integrated Design Environment for Early Stage Conceptual Design. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:754- [Conf]
- Hilary J. Kahn, Andy Carpenter, Nigel A. Whitaker
A Web-Based System for Assessing and Searching for Designs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:755- [Conf]
- Y. Tsiatouhas, Th. Haniotakis, Angela Arapoyanni, Dimitris Nikolos
A Versatile Built-In Self-Test Scheme for Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:756- [Conf]
- Dimitris Gizopoulos, Nektarios Kranitis, Mihalis Psarakis, Antonis M. Paschalis, Yervant Zorian
Effective Low Power BIST for Datapaths. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:757- [Conf]
- Dirk W. Hoffmann, Thomas Kropf
Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:758- [Conf]
- Jens Schönherr, Bernd Straube
Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:759- [Conf]
- Saeid Nooshabadi, Juan A. Montiel-Nelson, Antonio Núñez, Roberto Sarmiento, J. Sosa
A Single Phase Latch for High Speed GaAs Domino Circuits. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:760- [Conf]
- Alex Niemegeers, Gjalt G. de Jong
An Incremental Specification Flow for Real Time Embedded Systems. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:761- [Conf]
- Valery A. Vardanian, Liana B. Mirzoyan
Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:762- [Conf]
- Cecilia Metra, Michele Favalli, Bruno Riccò
On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:763- [Conf]
- Carsten Wegener, Michael Peter Kennedy
Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs. [Citation Graph (0, 0)][DBLP]
DATE, 2000, pp:765- [Conf]
|
