Conferences in DBLP
A. Dell'Acqua , M. Hansen , S. Inkinen , B. Lofstedt , J. P. Vanuxem , Christer Svensson , Jiren Yuan , H. Hentzell , L. Del Buono , J. David , J. F. Genat , H. Lebbolo , O. LeDortz , P. Nayman , A. Savoy-Navarro , R. Zitoun , Cesare Alippi , Luca Breveglieri , Luigi Dadda , Vincenzo Piuri , Fabio Salice , Mariagiovanna Sami , Renato Stefanelli , P. Cattaneo , G. Fumagalli , G. Goggi , S. Brigati , Umberto Gatti , Franco Maloberti , Guido Torelli , P. Carlson , A. Kerek , Goran Appelquist , S. Berglund , C. Bohm , Magnus Engström , N. Yamdagni , Rolf Sundblad , I. Höglund , S. T. Persson System Level Policies for Fault Tolerance Issues in the FERMI Project. [Citation Graph (0, 0)][DBLP ] Conf ] R. Rochet , Régis Leveugle , Gabriele Saucier Analysis and Comparison of Fault Tolerant FSM Architectures Based on SEC Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Liangkung Lin , G. Robert Redinbo Block Implementation of Fault-Tolerant LMS Adaptive FIR Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Hee Yong Youn , Kyung Ook Lee Fault-Tolerant Sorting Using VLSI Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Gian-Carlo Cardarilli , M. Di Zenzo , Pat O. Pistilli , Adelio Salsano A High Speed Reed-Solomon Encoder-Decoder for Fault Tolerant Solid State Disks. [Citation Graph (0, 0)][DBLP ] Conf ] Lisa Guerra , Miodrag Potkonjak , Jan M. Rabaey High Level Synthesis Techniques for Efficient Built-In-Self Repair. [Citation Graph (0, 0)][DBLP ] Conf ] Hannu Kari , Heikki Saikkonen , Fabrizio Lombardi Detection of Defective Media in Disks. [Citation Graph (0, 0)][DBLP ] Conf ] Hussain Al-Asaad , Elias S. Manolakos A Two-Phase Reconfiguration Strategy for Extracting Linear Arrays Out of Two-Dimensional Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Chor Ping Low , Hon Wai Leong On the Reconfiguration of Degradable VLSI/WSI Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Chouki Aktouf , Chantal Robach , Guy Mazaré , J. Johansson Functional Testing and Reconfiguration of MIMD Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Hideo Ito A Defect-Tolerant Design for WSI Interconnection Networks and Its Application to Hypercube. [Citation Graph (0, 0)][DBLP ] Conf ] José Salinas , Fabrizio Lombardi On the Reconfigurable Operation of Arrays with Defects for Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] A. Kerek Front-end Electronics in the Radiation Environment of LHC. [Citation Graph (0, 0)][DBLP ] Conf ] Víctor H. Champac , Antonio Rubio , Joan Figueras Analysis of the Floating Gate Defect in CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio Casimiro , M. Simões , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Experiments on Bridging Fault Analysis and Layout-Level DFT for CMOS Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Hua Xue , Chennian Di , Jochen A. G. Jess Fast Multi-Layer Critical Area Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Ferrati , Magneti Marelli TEh Reliability of the Integrated Circuits in Automotive Industry. [Citation Graph (0, 0)][DBLP ] Conf ] Randall S. Collica A Logistic Regression Yield Model for SRAM Bit Fail Patterns. [Citation Graph (0, 0)][DBLP ] Conf ] Charles H. Stapper , J. A. Patrick , R. J. Rosner Yield Model for ASIC and Processor Chips. [Citation Graph (0, 0)][DBLP ] Conf ] J. Crépeau , Claude Thibeault , Yvon Savaria Some Results on Yield and Local Design Rule Relaxation. [Citation Graph (0, 0)][DBLP ] Conf ] Frederic Duvivier , M. Rivier , B. Burtschy , J. J. Charlot Use of a Segmentation Technique to Analyze the Variability of the Yield of a Mature CMOS SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Zahava Koren , Israel Koren Does the Floorplan of a Chip Affect Its Yield? [Citation Graph (0, 0)][DBLP ] Conf ] Israel A. Wagner , Israel Koren An Interactive Yield Estimator as a VLSI CAD Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Venkat K. R. Chiluvuri , Israel Koren Topological Optimization of PLAs for Yield Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Eiji Fujiwara , Masaharu Tanaka A Defect-Tolerant WSI File Memory System Using Address Permutation Scheme for Spare Allocation. [Citation Graph (0, 0)][DBLP ] Conf ] Giacomo Buonanno , Franco Fummi , Donatella Sciuto Fault Detection in Sequential Circuits through Functional Testing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Rullán , F. C. Blom , J. Oliver , C. Ferrer Layout Level Design for Testability Strategy Applied to a CMOS Cell Library. [Citation Graph (0, 0)][DBLP ] Conf ] Michel Renovell , Joan Figueras Current Testing Viability in Dynamic CMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] David Wessels , Jon C. Muzio Probabilistic Identification of Critical Components for Circuit Delays. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Bombana , Giacomo Buonanno , Patrizia Cavalloro , Fabrizio Ferrandi , Donatella Sciuto , Giuseppe Zaza Reduction of Fault Detection Costs through Testable Design of Sequential Architectures with Signal Feedbacks. [Citation Graph (0, 0)][DBLP ] Conf ] Graham Frearson The T9000 Transputer: A Practical Example of the Application of Standard Test Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Egor S. Sogomonyan , Michael Gössel Design of Self-Parity Combinational Circuits for Self-testing and On-line Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaoling Sun , Micaela Serra Design and Implementation of a Merged On-Line and Off-Line Self Textable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Dah-Yea Wei , Jung Hwan Kim , T. R. N. Rao Complete Tests in Algorithm-Based Fault-Tolerant Matrix Operations on Processor Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Jien-Chung Lo , Eiji Fujiwara A Probabilistic Measurement for Totally Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Piero Olivo , Bruno Riccò Design Rules for CMOS Self Checking Circuits with Parametric Faults in the Functional Block. [Citation Graph (0, 0)][DBLP ] Conf ] Cecilia Metra , Michele Favalli , Piero Olivo , Bruno Riccò A Highly Testable 1-out-of-3 CMOS Checker. [Citation Graph (0, 0)][DBLP ] Conf ] Yuang-Ming Hsu , Earl E. Swartzlander Jr. VLSI Concurrent Error Correcting Adders and Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] D. Taylor , P. S. A. Evans , D. Marland Functional Testing of Linear Circuits Using Transient Response Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandra Fanni , Alessandro Giua , Enrico Sandoli Neural Networks for Multiple Fault Diagnosis in Analog Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] P. Nicolau , J. Barbosa , M. Saraiva , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Realistic Fault Analysis of CMOS Analog Building Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Sachdev Catastrophic Defects Oriented Testability Analysis of a Class AB Amplifier. [Citation Graph (0, 0)][DBLP ] Conf ] Nagendra Kumar , Philippe O. Pouliquen , Andreas G. Andreou Device Mismatch Limitations on the Performance of a Hamming Distance Classifier. [Citation Graph (0, 0)][DBLP ] Conf ] 