Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
1994 (conf/dft/1994)

1. Yinan N. Shen, Hannu Kari, S. S. Kim, Fabrizio Lombardi
   Scheduling Policies for Fault Tolerance in a VLSI Processor. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:1-9 [Conf]
   
2. Cristiana Bolchini, Giacomo Buonanno, Donatella Sciuto, Renato Stefanelli
   A CMOS Fault Tolerant Architecture for Swith-Level Faults. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:10-18 [Conf]
   
3. M. B. Alhaji-Hussaini, R. Mike Lea
   A Defect and Fault Tolerant Interconnection Network Strategy for WASP Devices. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:19-27 [Conf]
   
4. S. Goldberg, Shambhu J. Upadhyaya
   Implementation of a Gracefully Degradable Binary Tree in Programmable. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:28-36 [Conf]
   
5. Luigi Dadda, Vincenzo Piuri
   Fault-Tolerant Modular Convolves. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:37-45 [Conf]
   
6. C. Ferrer, D. Dateo, J. Oliver, Antonio Rubio, M. Rullán
   An Approach to the Development of a IDDQ Testable Cell Library. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:46-54 [Conf]
   
7. Zaifu Zhang, Robert D. McLeod, Witold Pedrycz
   Augmenting Scan Path SRLs with an XOR Network to Enhance Delay Fault Testing. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:55-64 [Conf]
   
8. A. J. Bishop, André Ivanov
   On the Testability of CMOS Feedback Amplifiers. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:65-73 [Conf]
   
9. Dah-Yea Wei, Jung Hwan Kim, T. R. N. Rao
   Roundoff Error-Free Tests in Algorithm-Based Fault Tolerant Matrix Operations on 2-D Processor Arrays. [Citation Graph (0, 0)][DBLP]
   DFT, 1994, pp:74-82 [Conf]
   
10. Charles H. Stapper, A. J. Rideout
    On Fractal Yield Models: A Statistical Paradox. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:83-87 [Conf]
    
11. Gerard A. Allan, Anthony J. Walton
    Efficient Critical Area Algorithms and Their Application to Yield Improvement and Test Strategies. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:88-96 [Conf]
    
12. Venkat K. R. Chiluvuri, Israel Koren, Jeffrey L. Burns
    The Effect of Wire Length Minimization on Yield. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:97-105 [Conf]
    
13. Glenn H. Chapman
    Laser Processes for Defect Correction in Large Area VLSI Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:106-114 [Conf]
    
14. Fabio Salice, Mariagiovanna Sami, Donatella Sciuto
    Synthesis of Multi-level Self-Checking Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:115-123 [Conf]
    
15. T. Bogue, Helmut Jürgensen, Michael Gössel
    Design of Cover Circuits for Monitoring the Output of a MISA. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:124-132 [Conf]
    
16. Cecilia Metra, Michele Favalli, Bruno Riccò
    CMOS Self Checking Circuits with Faulty Sequential Functional Block. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:133-141 [Conf]
    
17. Cecilia Metra, Michele Favalli, Bruno Riccò
    Highly Testable and Compact 1-out-of-n CMOS Checkers. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:142-150 [Conf]
    
18. Sihai Xiao, Xiaofa Shi, Guilang Feng, T. R. N. Rao
    Some Results on Improving the Code Length of SbEC-DED Codes. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:151-158 [Conf]
    
19. Yuang-Ming Hsu, Earl E. Swartzlander Jr.
    Reliability Estimation for Time Redundant Error Correcting Adders and Multipliers. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:159-167 [Conf]
    
20. Jie-Chung Lo
    A Fault-Tolerant Associative Approach to On-Line Memory Repair. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:168-176 [Conf]
    
21. Hideo Ito, Takashi Yagi
    Fault Tolerant Design Using Error Correcting Code for Multilayer Neural Networks. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:177-184 [Conf]
    
22. Rachid Kermouche, Yvon Savaria
    Defect and Fault Tolerant Scan Chains. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:185-193 [Conf]
    
23. Anuj Chandra, Rami G. Melhem
    Reconfiguration in 3D Meshes. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:194-202 [Conf]
    
24. Tong Liu, Fabrizio Lombardi
    On Soft Switch Programming for Reconfigurable Array Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:203-211 [Conf]
    
25. Susumu Horiguchi, Issei Numata
    A Self-Reconfiguration Architecture for Mesh Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:212-220 [Conf]
    
26. Weiping Shi
    A General Method to Design and Reconfigure Loop-Based Linear Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:221-229 [Conf]
    
27. Brenda S. Cantell, Randall S. Collica, José G. Ramírez
    Statistical analysis of Particle/Defect Data Experiments Using Poisson and Logistic Regression. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:230-238 [Conf]
    
28. Zhan Chen, Israel Koren
    A Yield Study of VLSI Adders. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:239-245 [Conf]
    
29. Kiyoshi Mori, Nam T. Nguyen, Dewey Keeton, Ross Burns
    Yield Enhancement with Particle Defects Reduction. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:246-253 [Conf]
    
30. Franco Fummi, Donatella Sciuto, Micaela Serra
    Test Generation for Stuck-at and Gate-Delay Faults in Sequential Circuits: A Mixed Functional/Structural Method. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:254-262 [Conf]
    
31. Antonio Casimiro, F. Conçalves, João Paulo Teixeira, Marcelino B. Santos
    On the Analysis of Routing Cells and Adjacency Faults in CMOS Digital Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:263-270 [Conf]
    
32. Régis Leveugle, R. Rochet, Gabriele Saucier
    Alternative Approaches to Fault Detection in FSMs. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:271-279 [Conf]
    
33. Claude Thibeault
    Using Fourier Analysis to Enhance IC Testability. [Citation Graph (0, 0)][DBLP]
    DFT, 1994, pp:280-298 [Conf]