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Conferences in DBLP

Defect and Fault Tolerance in VLSI Systems (dft)
2006 (conf/dft/2006)

  1. Krishnendu Chakrabarty
    Reconfiguration-Based Defect Tolerance for Microfluidic Biochips. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:- [Conf]
  2. David Heidel
    Single-Event-Upset Trends in Advanced CMOS Technologies. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:- [Conf]
  3. Ramyanshu Datta, Jacob A. Abraham, Abdulkadir Utku Diril, Abhijit Chatterjee, Kevin J. Nowka
    Adaptive Design for Performance-Optimized Robustness. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:3-11 [Conf]
  4. Tian Xia, Stephen Wyatt, Rupert Ho
    Employing On-Chip Jitter Test Circuit for Phase Locked Loop Self-Calibration. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:12-19 [Conf]
  5. Kristian Granhaug, Snorre Aunet
    Improving Yield and Defect Tolerance in Multifunction Subthreshold CMOS Gates. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:20-28 [Conf]
  6. V. Beiu, W. Ibrahim, Y. A. Alkhawwar, M. H. Sulieman
    Gate Failures Effectively Shape Multiplexing. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:29-40 [Conf]
  7. N. Devtaprasanna, A. Gunda, P. Krishnamurthy, Sudhakar M. Reddy, Irith Pomeranz
    Test Generation for Open Defects in CMOS Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:41-49 [Conf]
  8. Kyriakos Christou, Maria K. Michael, Spyros Tragoudas
    Implicit Critical PDF Test Generation with Maximal Test Efficiency. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:50-58 [Conf]
  9. Hangkyu Lee, Suriyaprakash Natarajan, Srinivas Patil, Irith Pomeranz
    Selecting High-Quality Delay Tests for Manufacturing Test and Debug. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:59-70 [Conf]
  10. Xiaojun Ma, Jing Huang, Cecilia Metra, Fabrizio Lombardi
    Testing Reversible 1D Arrays for Molecular QCA. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:71-79 [Conf]
  11. Minsu Choi, Myungsu Choi, Zachary D. Patitz, Nohpill Park
    Efficient and Robust Delay-Insensitive QCA (Quantum-Dot Cellular Automata) Design. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:80-88 [Conf]
  12. Byunghyun Jang, Yong-Bin Kim, Fabrizio Lombardi
    Error Tolerance of DNA Self-Assembly by Monomer Concentration Control. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:89-97 [Conf]
  13. Yadunandana Yellambalase, Minsu Choi, Yong-Bin Kim
    Inherited Redundancy and Configurability Utilization for Repairing Nanowire Crossbars with Clustered Defects. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:98-106 [Conf]
  14. Reza M. Rad, Mohammad Tehranipoor
    A Reconfiguration-based Defect Tolerance Method for Nanoscale Devices. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:107-118 [Conf]
  15. Sverre Wichlund, Frank Berntsen, Einar J. Aas
    Reducing ATE Bandwidth and memory requirements: A diagnosis friendly scan test response compactor. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:119-127 [Conf]
  16. Hamidreza Hashempour, Fabrizio Lombardi
    A Novel Methodology for Functional Test Data Compression. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:128-135 [Conf]
  17. Gang Zeng, Youhua Shi, Toshinori Takabatake, Masao Yanagisawa, Hideo Ito
    Low-Cost IP Core Test Using Multiple-Mode Loading Scan Chain and Scan Chain Clusters. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:136-144 [Conf]
  18. Geewhun Seok, Il-soo Lee, Tony Ambler, B. F. Womack
    An Efficient Scan Chain Partitioning Scheme with Reduction of Test Data under Routing Constraint. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:145-156 [Conf]
  19. Vijay K. Jain, Glenn H. Chapman
    Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:157-165 [Conf]
  20. Akhil Garg, Prashant Dubey
    Fuse Area Reduction based on Quantitative Yield Analysis and Effective Chip Cost. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:166-174 [Conf]
  21. Hiroyuki Ohde, Haruhiko Kaneko, Eiji Fujiwara
    Low-Density Triple-Erasure Correcting Codes for Dependable Distributed Storage Systems. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:175-183 [Conf]
  22. Gong Rui, Chen Wei, Liu Fang, Dai Kui, Wang Zhiying
    Modified Triple Modular Redundancy Structure based on Asynchronous Circuit Technique. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:184-196 [Conf]
  23. Yuejian Wu, André Ivanov
    Low Power SoC Memory BIST. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:197-205 [Conf]
  24. Avijit Dutta, Nur A. Touba
    Synthesis of Efficient Linear Test Pattern Generators. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:206-214 [Conf]
  25. Abhijit Jas, Yi-Shing Chang, Sreejit Chakravarty
    An Approach to Minimizing Functional Constraints. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:215-226 [Conf]
  26. Salvatore Pontarelli, Marco Ottavi, Vamsi Vankamamidi, Adelio Salsano, Fabrizio Lombardi
    Reliability Evaluation of Repairable/Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:227-235 [Conf]
  27. Xingguo Xiong, Yu-Liang Wu, Wen-Ben Jone
    Reliability Analysis of Self-Repairable MEMS Accelerometer. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:236-244 [Conf]
  28. Sanghoan Chang, Gwan Choi
    Timing Failure Analysis of Commercial CPUs Under Operating Stress. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:245-253 [Conf]
  29. André V. Fidalgo, Gustavo R. Alves, José M. Ferreira
    Real Time Fault Injection Using Enhanced OCD -- A Performance Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:254-264 [Conf]
  30. Maurizio Rebaudengo, Luca Sterpone, Massimo Violante, Cristiana Bolchini, Antonio Miele, Donatella Sciuto
    Combined software and hardware techniques for the design of reliable IP processors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:265-273 [Conf]
  31. Ilia Polian, Bernd Becker, Masato Nakasato, Satoshi Ohtake, Hideo Fujiwara
    Low-Cost Hardening of Image Processing Applications Against Soft Errors. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:274-279 [Conf]
  32. Carlos Arthur Lang Lisbôa, Luigi Carro, Matteo Sonza Reorda, Massimo Violante
    Online hardening of programs against SEUs and SETs. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:280-290 [Conf]
  33. Chuen-Song Chen, Jien-Chung Lo, Tian Xia
    Equivalent IDDQ Tests for Systems with Regulated Power Supply. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:291-299 [Conf]
  34. Ondrej Novák, Zdenek Plíva, Jiri Jenícek, Zbynek Mader, Michal Jarkovský
    Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:300-308 [Conf]
  35. Lei Fang, Michael S. Hsiao
    Bilateral Testing of Nano-scale Fault-tolerant Circuits. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:309-317 [Conf]
  36. Sandeep Dechu, Manoj Kumar Goparaju, Spyros Tragoudas
    A Metric of Tolerance for the Manufacturing Defects of Threshold Logic Gates. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:318-326 [Conf]
  37. Yoichi Sasaki, Kazuteru Namba, Hideo Ito
    Soft Error Masking Circuit and Latch Using Schmitt Trigger Circuit. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:327-335 [Conf]
  38. Ajoy Kumar Palit, Kishore K. Duganapalli, Walter Anheier
    Influence of Resistive Bridging Fault on Crosstalk Coupling Effects in On-Chip Aggressor-Victim Interconnects. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:336-344 [Conf]
  39. Á. Michels, L. Petroli, Carlos Arthur Lang Lisbôa, Fernanda Gusmão de Lima Kastensmidt, Luigi Carro
    SET Fault Tolerant Combinational Circuits Based on Majority Logic. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:345-352 [Conf]
  40. Yusuke Fukushima, Masaru Fukushi, Susumu Horiguchi
    An Improved Reconfiguration Method for Degradable Processor Arrays Using Genetic Algorithm. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:353-361 [Conf]
  41. Yu-Jen Huang, Da-Ming Chang, Jin-Fu Li
    A Built-In Redundancy-Analysis Scheme for Self-Repairable RAMs with Two-Level Redundancy. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:362-370 [Conf]
  42. Marco Ottavi, Salvatore Pontarelli, A. Leandri, Adelio Salsano
    Design and Evaluation of a Hardware on-line Program-Flow Checker for Embedded Microcontrollers. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:371-379 [Conf]
  43. Christian El Salloum, Andreas Steininger, Peter Tummeltshammer, Werner Harter
    Recovery Mechanisms for Dual Core Architectures. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:380-388 [Conf]
  44. Yasser Sedaghat, Seyed Ghassem Miremadi, Mahdi Fazeli
    A Software-Based Error Detection Technique Using Encoded Signatures. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:389-400 [Conf]
  45. Hiroshi Takahashi, Shuhei Kadoyama, Yoshinobu Higami, Yuzo Takamatsu, Koji Yamazaki, Takashi Aikyo, Yasuo Sato
    Effective Post-BIST Fault Diagnosis for Multiple Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:401-109 [Conf]
  46. Yukiya Miura, Jiro Kato
    Fault Diagnosis of Analog Circuits Based on Adaptive Test and Output Characteristics. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:410-418 [Conf]
  47. Irith Pomeranz, Sudhakar M. Reddy
    Scan-Based Delay Fault Tests for Diagnosis of Transition Faults. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:419-427 [Conf]
  48. Ying-Yen Chen, Jing-Jia Liou
    Enhancing Diagnosis Resolution For Delay Faults By Path Extension Method. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:428-438 [Conf]
  49. Jozsef Dudas, Cory Jung, Linda Wu, Glenn H. Chapman, Israel Koren, Zahava Koren
    On-Line Mapping of In-Field Defects in Image Sensor Arrays. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:439-447 [Conf]
  50. Michelle L. La Haye, Cory Jung, David Chen, Glenn H. Chapman, Jozsef Dudas
    Fault Tolerant Active Pixel Sensors in 0.18 and 0.35 Micron Technologies. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:448-456 [Conf]
  51. Cristian Grecu, André Ivanov, Res Saleh, Partha Pratim Pande
    NoC Interconnect Yield Improvement Using Crosspoint Redundancy. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:457-465 [Conf]
  52. Partha Pratim Pande, Amlan Ganguly, Brett Feero, Benjamin Belzer, Cristian Grecu
    Design of Low power & Reliable Networks on Chip through joint crosstalk avoidance and forward error correction coding. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:466-476 [Conf]
  53. Zhiyuan He, Zebo Peng, Petru Eles, Paul M. Rosinger, Bashir M. Al-Hashimi
    Thermal-Aware SoC Test Scheduling with Test Set Partitioning and Interleaving. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:477-485 [Conf]
  54. Fengming Zhang, Warren Necoechea, Peter Reiter, Yong-Bin Kim, Fabrizio Lombardi
    Load Board Designs Using Compound Dot Technique and Phase Detector for Hierarchical ATE Calibrations. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:486-494 [Conf]
  55. Xiaojun Ma, Fabrizio Lombardi
    Multi-Site and Multi-Probe Substrate Testing on an ATE. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:495-506 [Conf]
  56. Federico Rota, Shantanu Dutt, Sahithi Krishna
    Off-Chip Control Flow Checking of On-Chip Processor-Cache Instruction Stream. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:507-515 [Conf]
  57. Joonhyuk Yoo, Manoj Franklin
    The Filter Checker: An Active Verification Management Approach. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:516-524 [Conf]
  58. Nandakumar P. Venugopal, Nihal Shastry, Shambhu J. Upadhyaya
    Effect of Process Variation on the Performance of Phase Frequency Detector. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:525-534 [Conf]
  59. Di Mu, Tian Xia, Hao Zheng
    Data Dependent Jitter Characterization Based on Fourier Analysis. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:534-544 [Conf]
  60. Lushan Li, Ramalingam Sridhar, Shambhu J. Upadhyaya
    A 3-port Register File Design for Improved Fault Tolerance on Resistive Defects in Core-Cells. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:545-553 [Conf]
  61. Tadayoshi Horita, Takurou Murata, Itsuo Takanami
    A Multiple-Weight-and-Neuron-Fault Tolerant Digital Multilayer Neural Network. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:554-562 [Conf]
  62. M. Ferringer, G. Fuchs, A. Steininger, G. Kempf
    VLSI Implementation of a Fault-Tolerant Distributed Clock Generation. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:563-571 [Conf]
  63. Mehran Mozaffari Kermani, Arash Reyhani-Masoleh
    Parity-Based Fault Detection Architecture of S-box for Advanced Encryption Standard. [Citation Graph (0, 0)][DBLP]
    DFT, 2006, pp:572-580 [Conf]
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