Conferences in DBLP
Jordi Cortadella Combining Structural and Symbolic Methods for the Verification of Concurrent Systems. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:2-7 [Conf ] Jainendra Kumar , Carl Pixley Logic and Functional Verification in a Commercial Semiconductor Environment. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:8-15 [Conf ] Naoshi Uchihira How to Make Concurrent Programs Highly Reliable- More than State Space Analysis. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:16-23 [Conf ] Luciano Lavagno System-Level Design Models and Implementation Techniques. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:24-0 [Conf ] Bilung Lee , Edward A. Lee Hierarchical Concurrent Finite State Machines in Ptolemy. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:34-40 [Conf ] Radu Grosu , Gheorghe Stefanescu , Manfred Broy Visual Formalisms Revisited. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:41-51 [Conf ] Jean-René Beauvais , Roland Houdebine , Paul Le Guernic , Éric Rutten , Thierry Gautier A Translation of Statecharts into Signal Approach of Time, Interoperability. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:52-0 [Conf ] Tomohiro Yoneda , Yutaka Ohtsuka , Märt Saarepera Verification of Parameterized Asynchronous Circuits: A Case Study. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:64-74 [Conf ] Antti Valmari , Ilkka Kokkarinen Unbounded Verification Results by Finite-State Compositional Techniques: 10any States and Beyond. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:75-0 [Conf ] Dang Van Hung Modeling and Verification of Biphase Mark Protocolsin Duration Calculus Using PVS. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:88-98 [Conf ] Kazuhiro Nakamura , Satoshi Yamane Formal Verification of Real-Time Software by Symbolic Model-Checker. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:99-108 [Conf ] Antonio Cerone , David A. Kearney , George J. Milne Integrating the Verification of Timing, Performance and Correctness Properties of Concurrent Systems. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:109-119 [Conf ] Michael V. Goncharov , Alexander B. Smirnov , Nikolai Starodoubtsev , Ilya V. Klotchkov Timing Extensions of STG Model and a Method to Simulate Timed STG Behavior in VHDL Environment. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:120-0 [Conf ] Krzysztof Bilinski , Erik L. Dagless Efficient Approach to Symbolic State Exploration of Complex Parallel Controllers. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:132-142 [Conf ] Toshiyuki Miyamoto , Sadatoshi Kumagai Calculating Place Capacity for Petri Nets Using Unfoldings. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:143-151 [Conf ] Alex Kondratyev , Jordi Cortadella , Michael Kishinevsky , Luciano Lavagno , Alexander Taubin , Alexandre Yakovlev Identifying State Coding Conflicts in Asynchronous System Specifications Using Petri Net Unfoldings. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:152-0 [Conf ] Giovanna Di Marzo Serugendo , Nicolas Guelfi Using Object-Oriented Algebraic Nets for the Reverse Engineering of Java Programs: A Case Study. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:166-176 [Conf ] Jörg Desel , Ekkart Kindler Proving Correctness of Distributed Algorithms Using High-Level Petri Nets - A Case Study. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:177-186 [Conf ] Hagen Völzer Verifying Fault Tolerance of Distributed Algorithms Formally - An Example. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:187-0 [Conf ] Miroslav N. Velev , Randal E. Bryant Verification of Pipelined Microprocessors by Correspondence Checking in Symbolic Ternary Simulation. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:200-212 [Conf ] Radu Negulescu Event-Driven Verification of Switch-Level Correctness Concerns. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:213-0 [Conf ] Howard Bowman , Joost-Pieter Katoen A True Concurrency Semantics for ET-LOTOS. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:228-238 [Conf ] Raymond R. Devillers , Maciej Koutny Recursive Nets in the Box Algebra. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:239-249 [Conf ] Swarup Mohalik , Ramaswamy Ramanujam A Presentation of Regular Languages in the Assumption - Commitment Framework. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:250-0 [Conf ] Wil M. P. van der Aalst Modeling and Analyzing Interorganizational Workflows. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:262-272 [Conf ] Claudio Demartini , Riccardo Sisto A Java-based Formal Development Environment for Factory Communication Systems. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:273-281 [Conf ] Franz Huber , Sascha Molterer , Bernhard Schätz , Oscar Slotosch , Alexander Vilbig Traffic Lights - An AutoFocus Case Study. [Citation Graph (0, 0)][DBLP ] ACSD, 1998, pp:282-0 [Conf ]