Conferences in DBLP
J. Sundberg Music Technology and Audio Processing: Rall. or Accel. into the Millennium? [Citation Graph (0, 0)][DBLP ] Conf ] Bev Littlewood Two Heads Are Better Than One: Using Diversity to Make Software Dependable. [Citation Graph (0, 0)][DBLP ] Conf ] G. Turnbull Industrial Experience Report. [Citation Graph (0, 0)][DBLP ] Conf ] Matjaz Mulej The Law of Requisite Holism Systemic versus Reductionistic versus Complex Thinking. [Citation Graph (0, 0)][DBLP ] Conf ] G. Magnani The Role of the Improvement Manager. Critical Factors Affecting the Development of an Improvement Strategy: Leadership, Organization, Key-Process or Business Results? [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Decina The Future of Networking. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak Digital System Design: Architectures, Methods and Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Theo A. C. M. Claasen The Changing Semiconductor Industry: From Components to Silicon Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Peeter Ellervee , Ahmed Hemani , Miguel Miranda , Francky Catthoor Exploiting Data Transfer Locality in Memory Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Krzysztof Kuchcinski Synthesis of Distributed Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Radoslaw Szymanek , Krzysztof Kuchcinski Design Space Exploration in System Level Synthesis under Memory Constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Ki Leung , Adam Postula Specialized Processor for Channel Allocation in a Cellular Mobile Network. [Citation Graph (0, 0)][DBLP ] Conf ] Kimmo Kuusilinna , Pasi Liimatainen , Timo Hämäläinen , Jukka Saarinen Reconfiguration Mechanism for an IP Block Based Interconnection. [Citation Graph (0, 0)][DBLP ] Conf ] Mathias Kortke , Dirk Fimmel , Renate Merker Parallelization of Algorithms for a System of Digital Signal Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Claudio Sansoè , Francesco Gregoretti , Leonardo Maria Reyneri A Neuro-Fuzzy Real-Time Image Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] C. John Glossner , Stamatis Vassiliadis Delft-Java Dynamic Translation. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Hormigo , Julio Villalba , Emilio L. Zapata Arithmetic Unit for the Computation of Interval Elementary Functions. [Citation Graph (0, 0)][DBLP ] Conf ] Gil-Haeng Lee Issues of the State Information for Location and Information Policies in Distributed Load Balancing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Antonio Boluda , Fernando Pardo , Francisco Blasco , Joan Pelechano A Pipelined Reconfigurable Architecture for Visual-Based Navigation. [Citation Graph (0, 0)][DBLP ] Conf ] Jens Schönherr , Ingo Schreiber , Eva Fordran , Bernd Straube Hazard Checking in Pipelined Processor Designs Using Symbolic Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Wolfgang Günther Generation of Optimal Universal Logic Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Rawski , Lech Józwiak , Tadeusz Luba The Influence of the Number of Values in Sub-Functions on the Effectiveness and Efficiency of the Functional Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Mariusz Rawski , Lech Józwiak , Tadeusz Luba Efficient Input Support Selection for Sub-functions in Functional Decomposition Based on Information Relationship Measures. [Citation Graph (0, 0)][DBLP ] Conf ] Valeri Solovjev Refined CPLD Macrocell Architecture for the Effective FSM Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Rong Lin , Kevin E. Kerr , André S. Botha A Novel Approach for CMOS Parallel Counter Design. [Citation Graph (0, 0)][DBLP ] Conf ] Gloria Martínez , Germán Fabregat , Vicente Hernández A Systolic Library for Solving Matrix Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Luis Nunez , Claudia Feregrino , Simon Jones , Stephen Bateman The X-MatchLITE FPGA-Based Data Compressor. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Schwarz , Bärbel Mertsching , M. Brucke , Wolfgang Nebel , Jürgen Tchorz , Birger Kollmeier Implementing a Quantitative Model for the "Effective" Signal Processing in the Auditory System on a Dedicated Digital VLSI Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Kees-Jan van der Kolk , Ed F. Deprettere , Jeong-A. Lee A Floating Point Vectoring Algorithm Based on Fast Rotations. [Citation Graph (0, 0)][DBLP ] Conf ] Lech Józwiak , Artur Chojnacki Functional Decomposition based on Information Relationship Measures Extremely Effective and Efficient for Symmetric Functions. [Citation Graph (0, 0)][DBLP ] Conf ] José Alberto Espejo , Luis Entrena , Enrique San Millán , Emilio Olías Logic Restructuring for MUX-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Song Chen , Adam Postula , Lech Józwiak Synthesis of XOR Storage Schemes with Different Cost for Minimization of Memory Contention. [Citation Graph (0, 0)][DBLP ] Conf ] Toshinori Sato A Simulation Study of Pipelining and Decoupling a Dynamic Instruction Scheduling Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Lieven Eeckhout , Henk Neefs , Koenraad De Bosschere , Jan Van Campenhout Investigating the Implementation of a Block Structured Architecture in an Early Design Stage. [Citation Graph (0, 0)][DBLP ] Conf ] Asheesh Khare , Nicolae Savoiu , Ashok Halambi , Peter Grun , Nikil D. Dutt , Alexandru Nicolau V-SAT: A Visual Specification and Analysis Tool for System-On-Chip Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Gregorio Cappuccino , Giuseppe Cocorullo A Time-Domain Model for Power Dissipation of CMOS Buffers Driving Lossy Transmission Lines. [Citation Graph (0, 0)][DBLP ] Conf ] M. A. Sacristán , María Victoria Rodellar Biarge , A. Diaz , V. Garcia , Pedro Gómez Vilda A Reusable Inner Product Unit for DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Frédéric Mallet , Fernand Boéri Esterel and Java in an Object-Oriented Modelling and Simulation Framework for Heterogeneous Software and Hardware Systems The SEP Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Jang-Soo Lee , Won-Kee Hong , Shin-Dug Kim A Selective Compressed Memory System by On-Line Data Decompressing. [Citation Graph (0, 0)][DBLP ] Conf ] Li-San Li , Huang-Zhen Chun Lookahead Cache with Instruction Processing Unit for Filling Memory Gap. [Citation Graph (0, 0)][DBLP ] Conf ] Øyvind Strøm , Audun Klauseie , Einar J. Aas A Study of Dynamic Instruction Frequencies in Byte Compiled Java Programs. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Bautista , Antonio Núñez Design of Efficient SPARC Cores for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Hakenes , Yiannos Manoli A Segmented Gray Code for Low-Power Microcontroller Address Buses. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro De Gloria , Paolo Palma , Mauro Olivieri Delay-Insensitive Synthesis of the MCS 251 Microcontroller Core for Low Power Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Kreuzinger , Theo Ungerer Context-Switching Techniques for Decoupled Multithreaded Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Pawel Tomaszewicz , Andrzej Krasniewski Self-Testing of S-Compatible Test Units in User-Programmed FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Application-Dependent Testing of FPGA Delay Faults. [Citation Graph (0, 0)][DBLP ] Conf ] George Economakos , George K. Papakonstantinou Language Based Design Verification with Semantic Analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Dariusz Kania Two-Level Logic Synthesis on PAL-Based CPLD and FPGA Using Decomposition. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Rauscher , Dieter Klawan Results in Comparing Innovative Placement Heuristics. [Citation Graph (0, 0)][DBLP ] Conf ] Valeri Solovjev , Mariusz Chyzy The Universal Algorithm for Fitting Targeted to Complex Programmable Logic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos A. Kountouris , Christophe Wolinski High Level Pre-Synthesis Optimization Steps Using Hierarchical Conditional Dependency Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Flavius Gruian , Krzysztof Kuchcinski Low-Energy Directed Architecture Selection and Task Scheduling for System-Level Design. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Pop , Petru Eles , Zebo Peng An Improved Scheduling Technique for Time-Triggered Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino Region Compression: A New Scheme for Memory Energy Minimization in Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Luc Bianco , Michel Auguin , Alain Pegatoquet A Prototyping Method of Embedded Real Time Systems for Signal Processing Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Torrey Lewis , Marek A. Perkowski , Lech Józwiak Learning in Hardware: Architecture and Implementation of an FPGA-Based Rough Set Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Till Harbaum , Detlef Meier , Matthias Prinke , Martina Zitterbart Design of a Flexible Coprocessor Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Christof Teuscher , Jacques-Olivier Haenni , Héctor Fabio Restrepo , Eduardo Sanchez , Francisco J. Gómez A Tool for Teaching and Research on Computer Architecture and Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Dragan Jankovic , Radomir S. Stankovic Generic Implementation of DD Packages in MVL. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler Checking Integrity During Dynamic Reordering in Decision Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Rafal Rzechowski , Tadeusz Luba , Lech Józwiak Technology Driven Multilevel Logic Synthesis Based on Functional Decomposition into Gates. [Citation Graph (0, 0)][DBLP ] Conf ] Ireneusz Brzozowski , Andrzej Kos Minimization of Power Consumption in Digital Integrated Circuits by Reduction of Switching Activity. [Citation Graph (0, 0)][DBLP ] Conf ] F. Muller , Jean Paul Calvez , Dominique Heller , Olivier Pasquier An Interactive Modeling and Generation Tool for the Design of Hw/Sw Systems. [Citation Graph (0, 0)][DBLP ] Conf ] S. Barrios , J. López Heterogeneous Systems Design: A UML-Based Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Young Moo Lee , Kyu Ho Park Unified Modeling Graph for Specifying and Synthesizing Chip-Level Interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Francesco Curatelli , Leonardo Mangeruca , Marco Chirico A Message-Passing Communication Scheme for System Specification. [Citation Graph (0, 0)][DBLP ] Conf ] Claus Schneider Executable Specification for Multimedia Supporting Refinement and Architecture Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Mathias Sporer , Karlheinz Agsteiner , Dieter Monjau , Michael Schwaar Knowledge Based Specification and Modeling of Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Siddika Berna Örs , Ahmet Dervisoglu Modeling Bit Multiplication Blocks for DSP Applications Using VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Eiichirou Shigehara , Yoshinori Takeuchi , Masaharu Imai , Tsutomu Kimura Application of FHM-Based Design Method to Scalable 2-D DCT Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Grzegorz Kucharski , Wlodzimierz Wrona An Optimization of Simulation Time in the Hardware Accelerated VLSI Simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Marina Alonso , Vicente Santonja A New Destage Algorithm for Disk Cache: DOME. [Citation Graph (0, 0)][DBLP ] Conf ] Julio Sahuquillo , Ana Pont The Filter Cache: A Run-Time Cache Management Approach1. [Citation Graph (0, 0)][DBLP ] Conf ] Ryotaro Kobayashi , Yukihiro Ogawa , Hideki Ando , Toshio Shimada , Mitsuaki Iwata An On-Chip Multiprocessor Architecture with a Non-Blocking Synchronization Mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Lucian N. Vintan , Colin Egan Extending Correlation in Branch Prediction Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Tanguy Gilmont , Jean-Didier Legat , Jean-Jacques Quisquater Enhancing Security in the Memory Management Unit. [Citation Graph (0, 0)][DBLP ] Conf ] B. S. Visser A Framework for Retargetable Code Generation Using Simulated Annealing. [Citation Graph (0, 0)][DBLP ] Conf ] L. J. van Bokhoven , Jeroen Voeten , Marc Geilen Software Synthesis for System Level Design Using Process Execution Trees. [Citation Graph (0, 0)][DBLP ] Conf ] Gregor Polansek , Andrej Zemva , Andrej Trost HW/SW Co-Simulation of Target C++ Applications and Synthesizable HDL with Performance Estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Moya , Juan Carlos López , José Manuel Moya Evaluation of Design Space Exploration Strategies. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Bauer , Wolfgang Ecker , Renate Henftling , Andreas Zinn A Method for Accelerating Test Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Janusz Sosnowski , Piotr Gawkowski Tracing Fault Effects in System Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Wodey , Fabrice Baray Linking Codesign and Verification by Means of E-LOTOS FDT. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Kreiner , Christian Steger , Reinhold Weiss A Hardware/Software Cosimulation Environment for DSP Applications. [Citation Graph (0, 0)][DBLP ] Conf ] P. H. A. van der Putten , Jeroen Voeten , Marc Geilen , M. P. J. Stevens System Level Models for Real-Time Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Olga Peñalba , José M. Mendías , Román Hermida A Unified Algorithm for Mutual Exclusiveness Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Felipe Fernández , Ángel Sánchez Application of Multidimensional Retiming and Matroid Theory to DSP Algorithm Parallelization. [Citation Graph (0, 0)][DBLP ] Conf ] Walter Lange , Wolfgang Rosenstiel VHDL Description and High-Level Synthesis of an ATM Layer Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Howard Workshop Chair Introduction: Music Technology and Audio Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Andy Hunt , Ross Kirk Radical User Interfaces for Real-Time Control. [Citation Graph (0, 0)][DBLP ] Conf ] M. Das , David M. Howard , Stephen L. Smith Motion Curves in Music: The Statistical Analysis of Midi Data. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Anderson Using Music Performance Software with Flexible Control Interfaces for Live Performance by Severely Disabled Musicians. [Citation Graph (0, 0)][DBLP ] Conf ] A. Lassauniere , J. Marchant , A. Close , G. E. Tewkesbury , D. A. Sanders A New Music Technology System to Teach Music. [Citation Graph (0, 0)][DBLP ] Conf ] Jon Maslin , Elizabeth Lyon Project Patron: Exploiting a Digital Library for the Performing Arts. [Citation Graph (0, 0)][DBLP ] Conf ] Paul E. Garner , David M. Howard Distance Learning Support for Teaching Musical Temperament. [Citation Graph (0, 0)][DBLP ] Conf ] Bob Lawlor , A. D. Fagan A Novel Efficient Algorithm for Music Transposition. [Citation Graph (0, 0)][DBLP ] Conf ] James A. S. Angus "Perfect" Audio Signal Processing using Finite Field Transforms. [Citation Graph (0, 0)][DBLP ] Conf ] George Tzanetakis , Perry R. Cook A Framework for Audio Analysis based on Classification and Temporal Segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Gibson , David M. Howard , Andrew M. Tyrrell A Parallel Processing System for Polyphonic Singing Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Kahlin , Sten Ternström The Chorus Effect Revisited: Experiments in Frequency-Domain Analysis and Simulation of Ensemble Sounds. [Citation Graph (0, 0)][DBLP ] Conf ] David M. Howard Digital Waveguide Modelling of Room Acoustics: Comparing Mesh Topologies. [Citation Graph (0, 0)][DBLP ] Conf ] Julian M. Bass Workshop Chair Introduction: Dependable Computing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Geert Deconinck , Vincenzo De Florio , Rudy Lauwereins , Ronnie Belmans A Software Library, A Control Backbone and User-Specified Recovery Strategies to Enhance the Dependability of Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Hiller Error Recovery using Forced Validity Assisted by Executable Assertions for Error Detection: An Experimental Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] G. Latif-Shabgahi , Stuart Bennett Adaptive Majority Voter: A Novel Voting Algorithm for Real-Time Fault-Tolerant Control Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jochen Kreuzinger , R. Marston , Theo Ungerer , Uwe Brinkschulte , C. Krakowski The Komodo Project: Thread-based Event Handling Supported by a Multithreaded Java Microcontroller. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew M. Tyrrell Computer Know Thy Self!: A Biological Way to Look at Fault-Tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Yudi Purwantoro , Stuart Bennett Decomposition Technique for Integrated Dependability Evaluation of Hardware-Software Systems Using Stochastic Activity Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Maisaa Khalil , Oum-El-Kheir Benkahla , Chantal Robach An Experimental Comparison of Software Diagnosis Methods. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Romano , Antonio Coronato , Antonino Mazzeo , Nicola Mazzocca A Design Tool for Dependable Video on Demand Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Gerhard Ghroust Workshop Chair Introduction: Software Process and Product Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Yingxu Wang , Graham King , Hakan Wickberg , Alec Dorling What the Softward Industry Says about the Practices Modelled in Current Softward Process Models? [Citation Graph (0, 0)][DBLP ] Conf ] Helen Sharp , Mark Woodman , Fiona Hovenden , Hugh Robinson The Role of 'Culture' in Successful Software Process Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Brian W. Chatters , Peter Henderson , Chris Rostron An Experiment to Improve Cost Estimation and Project Tracking for Software and Systems Integration Projects. [Citation Graph (0, 0)][DBLP ] Conf ] Minna Nättinen , Tua Rahikkala , Antti Välimäki Experiences from the Pilot Operation and Commissioning Phase of a SCM Process Improvement Program. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Fernand Tiako , Jean-Claude Derniame PSEEs Modelling for Supporting and Improving Collaborative Joint Software Development Projects. [Citation Graph (0, 0)][DBLP ] Conf ] Hareton K. N. Leung A Tool for Testing Hypermedia Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ayça Tarhan , Elif Demirörs , Onur Demirörs A Distributed Tool for Commitment Specification and Management. [Citation Graph (0, 0)][DBLP ] Conf ] Karl Rege Design Patterns for Component-Oriented Software Development. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg R. Mühlbacher , Peter R. Dietmüller , Markus Jöbstl Extendable Object Visualisation for Software Reengineering. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Oliver , Stuart Kent Validation of Object Oriented Models using Animation. [Citation Graph (0, 0)][DBLP ] Conf ] W. Lam , V. Shankararaman Requirements Change: A Dissection of Management Issues. [Citation Graph (0, 0)][DBLP ] Conf ] José Parets-Llorca , Paul Grünbacher Capturing, Negotiating, and Evolving System Requirements: Bridging WinWin and the UML. [Citation Graph (0, 0)][DBLP ] Conf ] Ivica Crnkovic , Peter J. Funk , Magnus Larsson Processing Requirements by Software Configuration Management. [Citation Graph (0, 0)][DBLP ] Conf ] Yingxu Wang , Alec Dorling , Hakan Wickberg , Graham King Experience in Comparative Process Assessment with Multi-Process-Models. [Citation Graph (0, 0)][DBLP ] Conf ] Philipp Jocham , Christian Kreiner A Lean Metric Acquisition and Presentation Environment for the Assessment of a Test Process Improvement Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Jussi Ronkainen , Tua Rahikkala , Rod Blackwood Automating SCM Metric Data Collection and Analysis in Virtual Software Corporations. [Citation Graph (0, 0)][DBLP ] Conf ] Hareton K. N. Leung , Connie Poon Multi-Agent Environment for Software Quality Assurance, AUTOQ. [Citation Graph (0, 0)][DBLP ] Conf ] Frédéric Patricelli Workshop Chair Introduction: Multimedia and Telecommunications. [Citation Graph (0, 0)][DBLP ] Conf ] Enhong Chen , Xufa Wang Semi-Structured Data Extraction and Schema Knowledge Mining. [Citation Graph (0, 0)][DBLP ] Conf ] E. A. Hakkennes , Stamatis Vassiliadis Hardwired Paeth Codec for Portable Network Graphics (PNG). [Citation Graph (0, 0)][DBLP ] Conf ] Johannes Peltola , Johan Plomp , Tapio Seppänen A Dictionary-Adaptive Speech Driven User Interface for a Distributed Multimedia Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Perfecto Mariño , Miguel Angel Domínguez , Francisco Poza , Juan B. Nogueira Design of Distributed System Protocols based on Standard FDL's. [Citation Graph (0, 0)][DBLP ] Conf ] J. M. Arco , A. Martínez , B. Alarcos , A. García , Daniel Meziat Carrying ATM Cells over Ethernet. [Citation Graph (0, 0)][DBLP ] Conf ] Alessio Bechini , Raffaele Lapadula , Cosimo Antonio Prete Dealing with Non-Determinism in Communications within Java Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Timo Hämäläinen Delay Performance Measurements in Multimedia Switching. [Citation Graph (0, 0)][DBLP ] Conf ] Juanjo Noguera , Rosa M. Badia , Jordi Domingo-Pascual , Josep Solé-Pareta Reconfigurable Computing: An Innovative Solution for Multimedia and Telecommunication Networks Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Han Namgoong , Myung-Joon Kim Improved Hard Acknowledgement Deadline Protocol in Real-Time RPC. [Citation Graph (0, 0)][DBLP ] Conf ] Pierpaolo Baglietto , A. L. Frisiani Combining Motion Estimation with Feature Extraction in MPEG Video Coders. [Citation Graph (0, 0)][DBLP ] Conf ] S. A. Karkanis , George D. Magoulas , Maria Grigoriadou , Dimitris A. Karras Neural Network based Textural Labeling of Images in Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitrios I. Rigas , D. Hopwood , Dave Memery Communicating Spatial Information via a Multimedia-Auditory Interface. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Woodman , Josie Taylor Balancing the Multimedia Mix in a Large Scale Distance Education Course. [Citation Graph (0, 0)][DBLP ] Conf ] Reinhard Rauscher , Frank Bohnsack Results of an Elliptic-Curve-Approach for Use in Cryptosystems. [Citation Graph (0, 0)][DBLP ] Conf ] Djamshid Tavangarian , Ferenc Vajda Workshop Chair Introduction : Special Session on Network Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Christoforos Panayiotou , George Samaras , Evaggelia Pitoura , Paraskevas Evripidou Parallel Computing using Java Mobile Agents. [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio Giordano , Mario Mango Furnari , Francesco Vitobello PVM Parameter Tuning to Improve Communication in Distributed Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Koranne A Distributed Algorithm for k-way Graph Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Marcus O'Connell , Paddy Nixon JFS: A Secure Distributed File System for Network Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Rafael Corchuelo , David Ruiz , Miguel Toro , Antonio Ruiz Cortés Implementing Multiparty Interactions on a Network Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Michael May Locust - A Brokerage System for Accessing Idle Ressources for Web-Computing. [Citation Graph (0, 0)][DBLP ] Conf ] 