Conferences in DBLP

Formal Methods in Computer-Aided Design (FMCAD) (fmcad)
2006 (conf/fmcad/2006)

1. Tilman Glökler, Jason Baumgartner, Devi Shanmugam, A. E. (Rick) Seigler, Gary A. Van Huben, Barinjato Ramanandray, Hari Mony, Paul Roessler
   Enabling Large-Scale Pervasive Logic Verification through Multi-Algorithmic Formal Reasoning. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:3-10 [Conf]
   
2. Zurab Khasidashvili, Marcelo Skaba, Daher Kaiss, Ziyad Hanna
   Post-reboot Equivalence and Compositional Verification of Hardware. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:11-18 [Conf]
   
3. Sava Krstic, Jordi Cortadella, Michael Kishinevsky, John O'Leary
   Synchronous Elastic Networks. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:19-30 [Conf]
   
4. Hyondeuk Kim, Fabio Somenzi
   Finite Instantiations for Integer Difference Logic. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:31-38 [Conf]
   
5. Éric Grégoire, Bertrand Mazure, Cédric Piette
   Tracking MUSes and Strict Inconsistent Covers. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:39-46 [Conf]
   
6. Hossein M. Sheini, Karem A. Sakallah
   Ario: A Linear Integer Arithmetic Logic Solver. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:47-48 [Conf]
   
7. Cameron Brien, Sharad Malik
   Understanding the Dynamic Behavior of Modern DPLL SAT Solvers through Visual Analysis. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:49-50 [Conf]
   
8. Byron Cook, Daniel Kroening, Natasha Sharygina
   Over-Approximating Boolean Programs with Unbounded Thread Creation. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:53-59 [Conf]
   
9. Neha Rungta, Eric G. Mercer
   An Improved Distance Heuristic Function for Directed Software Model Checking. [Citation Graph (0, 0)][DBLP]
   FMCAD, 2006, pp:60-67 [Conf]
   
10. Amir Hossein Ghamarian, Marc Geilen, Twan Basten, Bart D. Theelen, Mohammad Reza Mousavi, Sander Stuijk
    Liveness and Boundedness of Synchronous Data Flow Graphs. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:68-75 [Conf]
    
11. Johannes Faber, Roland Meyer
    Model Checking Data-Dependent Real-Time Properties of the European Train Control System. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:76-77 [Conf]
    
12. Xiaofang Chen, Yu Yang, Ganesh Gopalakrishnan, Ching-Tsun Chou
    Reducing Verification Complexity of a Multicore Coherence Protocol Using Assume/Guarantee. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:81-88 [Conf]
    
13. Florian Pigorsch, Christoph Scholl, Stefan Disch
    Advanced Unbounded Model Checking Based on AIGs, BDD Sweeping, And Quantifier Scheduling. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:89-96 [Conf]
    
14. Ashish Darbari
    Symmetry Reduction for STE Model Checking. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:97-105 [Conf]
    
15. Shiva Nejati, Mihaela Gheorghiu, Marsha Chechik
    Thorough Checking Revisited. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:106-116 [Conf]
    
16. Barbara Jobstmann, Roderick Bloem
    Optimizations for LTL Synthesis. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:117-124 [Conf]
    
17. Alessandro Cimatti, Marco Roveri, Simone Semprini, Stefano Tonetta
    From PSL to NBA: a Modular Symbolic Encoding. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:125-133 [Conf]
    
18. Sagar Chaki, Nishant Sinha
    Assume-Guarantee Reasoning for Deadlock. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:134-144 [Conf]
    
19. Husam Abu-Haimed, David L. Dill, Sergey Berezin
    A Refinement Method for Validity Checking of Quantified First-Order Formulas in Hardware Verification. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:145-152 [Conf]
    
20. Michael J. C. Gordon, James Reynolds, Warren A. Hunt Jr., Matt Kaufmann
    An Integration of HOL and ACL2. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:153-160 [Conf]
    
21. Jun Sawada, Erik Reeber
    ACL2SIX: A Hint used to Integrate a Theorem Prover and an Automated Verification Tool. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:161-170 [Conf]
    
22. C. Helmstetter, Florence Maraninchi, Laurent Maillet-Contoz, Matthieu Moy
    Automatic Generation of Schedulings for Improving the Test Coverage of Systems-on-a-Chip. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:171-178 [Conf]
    
23. Namrata Shekhar, Priyank Kalla, M. Brandon Meredith, Florian Enescu
    Simulation Bounds for Equivalence Verification of Arithmetic Datapaths with Finite Word-Length Operands. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:179-186 [Conf]
    
24. Haja Moinudeen, Ali Habibi, Sofiène Tahar
    Design for Verification of the PCI-X Bus. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:187-188 [Conf]
    
25. Abu Nasser M. Abdullah, Behzad Akbarpour, Sofiène Tahar
    Formal Analysis and Verification of an OFDM Modem Design using HOL. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:189-190 [Conf]
    
26. Julien Schmaltz
    A Formal Model of Lower System Layers. [Citation Graph (0, 0)][DBLP]
    FMCAD, 2006, pp:191-192 [Conf]