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Conferences in DBLP

Symposium on Field Programmable Gate Arrays (FPGA) (fpga)
2003 (conf/fpga/2003)

  1. Noha Kafafi, Kimberly Bozman, Steven J. E. Wilton
    Architectures and algorithms for synthesizable embedded programmable logic cores. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:3-11 [Conf]
  2. David M. Lewis, Vaughn Betz, David Jefferson, Andy Lee, Christopher Lane, Paul Leventis, Sandy Marquardt, Cameron McClintock, Bruce Pedersen, Giles Powell, Srinivas Reddy, Chris Wysocki, Richard Cliff, Jonathan Rose
    The StratixTM routing and logic architecture. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:12-20 [Conf]
  3. Andrea Lodi, Mario Toma, Fabio Campi
    A pipelined configurable gate array for embedded processors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:21-30 [Conf]
  4. Michael G. Wrighton, André DeHon
    Hardware-assisted simulated annealing with application for fast FPGA placement. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:33-42 [Conf]
  5. Pak K. Chan, Martine D. F. Schlag
    Parallel placement for field-programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:43-50 [Conf]
  6. Wai-Kei Mak
    I/O placement for FPGAs with multiple I/O standards. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:51-57 [Conf]
  7. Seokjin Lee, Hua Xiang, D. F. Wong, Richard Y. Sun
    Wire type assignment for FPGA routing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:61-67 [Conf]
  8. Akshay Sharma, Carl Ebeling, Scott Hauck
    PipeRoute: a pipelining-aware router for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:68-77 [Conf]
  9. Randy Huang, John Wawrzynek, André DeHon
    Stochastic, spatial routing for hypergraphs, trees, and meshes. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:78-87 [Conf]
  10. Chen Chang, Kimmo Kuusilinna, Brian C. Richards, Robert W. Brodersen
    Implementation of BEE: a real-time large-scale hardware emulation engine. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:91-99 [Conf]
  11. Joydeep Ray, James C. Hoe
    High-level modeling and FPGA prototyping of microprocessors. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:100-107 [Conf]
  12. Fernanda Lima, Luigi Carro, Ricardo Augusto da Luz Reis
    Reducing pin and area overhead in fault-tolerant FPGA-based designs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:108-117 [Conf]
  13. Jong-Ru Guo, Chao You, Kuan Zhou, Bryan S. Goda, Russell P. Kraft, John F. McDonald
    A scalable 2 V, 20 GHz FPGA using SiGe HBT BiCMOS technology. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:145-153 [Conf]
  14. Raphael Rubin, André DeHon
    Design of FPGA interconnect for multilevel metalization. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:154-163 [Conf]
  15. Ketan Padalia, Ryan Fung, Mark Bourgeault, Aaron Egier, Jonathan Rose
    Automatic transistor and physical design of FPGA tiles from an architectural specification. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:164-172 [Conf]
  16. Fei Li, Deming Chen, Lei He, Jason Cong
    Architecture evaluation for power-efficient FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:175-184 [Conf]
  17. Nicholas Weaver, Yury Markovskiy, Yatish Patel, John Wawrzynek
    Post-placement C-slow retiming for the xilinx virtex FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:185-194 [Conf]
  18. Katarzyna Leijten-Nowak, Jef L. van Meerbergen
    An FPGA architecture with enhanced datapath functionality. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:195-204 [Conf]
  19. Kimmo U. Järvinen, Matti Tommiska, Jorma Skyttä
    A fully pipelined memoryless 17.8 Gbps AES-128 encryptor. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:207-215 [Conf]
  20. François-Xavier Standaert, Gaël Rouvroy, Jean-Jacques Quisquater, Jean-Didier Legat
    A methodology to implement block ciphers in reconfigurable hardware and its application to fast and compact AES RIJNDAEL. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:216-224 [Conf]
  21. Seonil Choi, Ronald Scrofano, Viktor K. Prasanna, Ju-wook Jang
    Energy-efficient signal processing using FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:225-234 [Conf]
  22. M. A. Hannan Bin Azhar, Keith R. Dimond
    FPGA-based design of an evolutionary controller for collision-free robot navigation. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:237- [Conf]
  23. Prithviraj Banerjee, Vikram Saxena, J. R. Uribe, Malay Haldar, Anshuman Nayak, Victor Kim, Debabrata Bagchi, Satrajit Pal, Nikhil Tripathi, R. Anderson
    Making area-performance tradeoffs at the high level using the AccelFPGA compiler for FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:237- [Conf]
  24. Sanat Kamal Bahl, Jim Plusquellic
    FPGA implementation of a fast Hadamard transformer for WCDMA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:237- [Conf]
  25. Khaled Benkrid, S. Belkacemi, Danny Crookes
    A logic based approach to hardware abstraction. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:238- [Conf]
  26. Abdsamad Benkrid, Danny Crookes, Khaled Benkrid
    Design framework for the implementation of the 2-D orthogonal discrete wavelet transform on FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:238- [Conf]
  27. Khaled Benkrid, S. Sukhsawas, Danny Crookes, S. Belkacemi
    A single-FPGA implementation of image connected component labelling. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:238- [Conf]
  28. Sebastien Bilavarn, Guy Gogniat, Jean Luc Philippe
    An estimation and exploration methodology from system-level specifications: application to FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:239- [Conf]
  29. Stephan Bingemer, Peter Zipf, Manfred Glesner
    A granularity-based classification model for systems-on-a-chip. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:239- [Conf]
  30. Vanderlei Bonato, Rolf Fredi Molz, João Carlos Furtado, Marcos Flôres Ferrão, Fernando Gehm Moraes
    Design of a fingerprint system using a hardware/software environment. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:240- [Conf]
  31. Elaheh Bozorgzadeh, Majid Sarrafzadeh
    Customized regular channel design in FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:240- [Conf]
  32. Katherine Compton, Scott Hauck
    Track placement: orchestrating routing structures to maximize routability. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:241- [Conf]
  33. Joan Carletta, Robert J. Veillette, Frederick W. Krach, Zhengwei Fang
    Implementation of digital fixed-point approximations to continuous-time IIR filters. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:241- [Conf]
  34. Mehrdad Eslami Dehkordi, Stephen Dean Brown
    Recursive circuit clustering for minimum delay and area. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:242- [Conf]
  35. Pedro C. Diniz, Joonseok Park
    Using FPGAs for data and reorganization engines: preliminary results for spatial pointer-based data structures. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:242- [Conf]
  36. Hossam A. ElGindy, George Ferizis
    On hiding latency in reconfigurable systems: the case of merge-sort for an FPGA-based system. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:242- [Conf]
  37. Binlin Guo, Jiarong Tong
    A SC-based novel configurable analog cell. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  38. Yongquan Fan, Zeljko Zilic
    Testing for bit error rate in FPGA communication interfaces. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  39. Soheil Ghiasi, Karlene Nguyen, Elaheh Bozorgzadeh, Majid Sarrafzadeh
    On computation and resource management in an FPGA-based computation environment. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:243- [Conf]
  40. Frank Honoré, Benton H. Calhoun, Anantha Chandrakasan
    Power-aware architectures and circuits for FPGA-based signal processing. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:244- [Conf]
  41. Adrian J. Hilton, Gemma Townson, Jon G. Hall
    FPGAs in critical hardware/software systems. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:244- [Conf]
  42. Alex K. Jones, Prithviraj Banerjee
    An automated and power-aware framework for utilization of IP cores in hardware generated from C descriptions targeting FPGAs. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:244- [Conf]
  43. Fatih Kocan
    Reconfigurable randomized K-way graph partitioning. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:245- [Conf]
  44. Paul D. Kundarewich, Jonathan Rose
    Synthetic circuit generation using clustering and iteration. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:245- [Conf]
  45. Parag K. Lala, B. Kiran Kumar
    An FPGA architecture with built-in error correction capability. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:245- [Conf]
  46. Federico Quaglio, Maurizio Martina, Fabrizio Vacca, Guido Masera, Andrea Molino, Gianluca Piccinini, Maurizio Zamboni
    Wireless sensor networks: a power-scalable motion estimation IP for hybrid video coding. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:246- [Conf]
  47. Zdenek Pohl, Rudolf Matousek, Jiri Kadlec, Milan Tichý, Miroslav Lícko
    Lattice adaptive filter implementation for FPGA. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:246- [Conf]
  48. Gaël Rouvroy, François-Xavier Standaert, Jean-Jacques Quisquater, Jean-Didier Legat
    Design strategies and modified descriptions to optimize cipher FPGA implementations: fast and compact results for DES and triple-DES. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:247- [Conf]
  49. Peter Suaris, Dongsheng Wang, Pei-Ning Guo, Nan-Chi Chou
    A physical retiming algorithm for field programmable gate arrays. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:247- [Conf]
  50. Kuan Zhou, Michael Chu, Chao You, Jong-Ru Guo, Channakeshav, John Mayega, John F. McDonald, Russell P. Kraft, Bryan S. Goda
    A four-bit full adder implemented on fast SiGe FPGAs with novel power control scheme. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:248- [Conf]
  51. Mehdi Baradaran Tahoori
    A high resolution diagnosis technique for open and short defects in FPGA interconnects. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:248- [Conf]
  52. Mehdi Baradaran Tahoori
    Application-dependent testing of FPGAs for bridging faults. [Citation Graph (0, 0)][DBLP]
    FPGA, 2003, pp:248- [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
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