Conferences in DBLP
Julio Faura , Juan Manuel Moreno , Miguel Angel Aguirre Echánove , Phuoc van Duong , Josep Maria Insenser Multicontext dynamic reconfiguration and real time probing on a novel mixed signal programmable device with on-chip microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Toshiaki Miyazaki , Atsushi Takahara , Masaru Katayama , Takahiro Murooka , Takaki Ichimori , Ken-nosuke Fukami , Akihiro Tsutsui , Kazuhiro Hayashi CAD-oriented FPGA and dedicated CAD system for telecommunications. [Citation Graph (0, 0)][DBLP ] Conf ] Miriam Leeser , Waleed Meleis , Mankuan Michael Vai , Paul M. Zavracky Rothko: A three dimensional FPGA architecture, its fabrication, and design tools. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon McGregor , Patrick Lysaght Extending dynamic circuit switching to meet the challenges of new FPGA architectures. [Citation Graph (0, 0)][DBLP ] Conf ] David Robinson , Patrick Lysaght , Gordon McGregor , Hugh Dick Performance evaluation of a full speed PCI initiator and target subsystem using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Toan Do , Holger Kropp , M. Schwiegershausen , Peter Pirsch Implementation of pipelined multipliers on Xilinx FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Stuart Nisbet , Steve Guccione The XC6200DS development system. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo I. Boemo , Sergio López-Buedo Thermal monitoring on FPGAs using ring-oscillators. [Citation Graph (0, 0)][DBLP ] Conf ] Igor Kostarnov , Steve Morley , Javed Osmany , Charlie Solomon A reconfigurable approach to low cost media processing. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick I. Mackinlay , Peter Y. K. Cheung , Wayne Luk , Richard Sandiford Riley-2: A flexible platform for codesign and dynamic reconfigurable computing research. [Citation Graph (0, 0)][DBLP ] Conf ] Brian Kahne , Peter M. Athanas Stream synthesis for a wormhole run-time reconfigurable platform. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Luk , Nabeel Shirazi , Shaori Guo , Peter Y. K. Cheung Pipeline morphing and virtual pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Barry Rising , Max van Daalen , Peter Burge , John Shawe-Taylor Parallel Graph colouring using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver Diessel , Hossam A. ElGindy Run-time compaction of FPGA designs. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Emmert , Dinesh Bhatia Partial reconfiguration of FPGA mapped designs with applications to fault tolerance and yield enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Leonard , William H. Mangione-Smith A case study of partially evaluated hardware circuits: Key-specific DES. [Citation Graph (0, 0)][DBLP ] Conf ] Rob Payne Run-time parameterised circuits for the Xilinx XC6200. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner Automatc identification of swappable logic units in XC6200 circuitry. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Lysaght Towards an expert system for a priori estimation of reconfiguration latency in dynamically reconfigurable logic. [Citation Graph (0, 0)][DBLP ] Conf ] Brad L. Hutchings Exploiting reconfigurability through domain-specific systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michal Servít , Kang Yi Technology mapping by binate covering. [Citation Graph (0, 0)][DBLP ] Conf ] Vaughn Betz , Jonathan Rose VPR: A new packing, placement and routing tool for FPGA research. [Citation Graph (0, 0)][DBLP ] Conf ] Maurice Kilavuka Inuani , Jonathan Saul Technology mapping of heterogeneous LUT-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Feske , Sven Mulka , Manfred Koegst , Günter Elst Technology-driven FSM partitioning for synthesis of large sequential circuits targeting lookup-table based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Xiaochun Lin , Erik L. Dagless , Aiguo Lu Technology mapping of LUT based FPGAs for delay optimisation. [Citation Graph (0, 0)][DBLP ] Conf ] S. J. B. Acock , Keith R. Dimond Automatic mapping of algorithms onto multiple FPGA-SRAM modules. [Citation Graph (0, 0)][DBLP ] Conf ] R. Bruce Maunder , Zoran A. Salcic , George G. Coghill FPLD HDL synthesis employing high-level evolutionary algorithm optimisation. [Citation Graph (0, 0)][DBLP ] Conf ] Anton V. Chichkov , Carlos Beltrán Almeida A hardware/software partitioning algorithm for custom computing machines. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Lechner , Steve Guccione The Java environment for reconfigurable computing. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Jürgen Becker , Michael Herz , Ulrich Nageldinger Data scheduling to increase performance of parallel accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Kress , Reiner W. Hartenstein , Ulrich Nageldinger An operating system for custom computing machines based on the Xputer paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Dandalis , Viktor K. Prasanna Fast parallel implementation of DFT using configurable devices. [Citation Graph (0, 0)][DBLP ] Conf ] David Greenfield , Caleb Crome , Martin S. Won , Doug Amos Enhancing fixed point DSP processor performance by adding CPLDs as coprocessing elements. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Shand A case study of algorithm implementation in reconfigurable hardware and software. [Citation Graph (0, 0)][DBLP ] Conf ] Anjit Sekhar Chaudhuri , Peter Y. K. Cheung , Wayne Luk A reconfigurable data-localised array for morphological algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] B. Bramer , D. Chauham , M. K. Ibrahim , A. Aggoun Virtual radix array processors (V-RaAP). [Citation Graph (0, 0)][DBLP ] Conf ] T. Mathews , S. G. Gibb , Laurence E. Turner , Peter J. W. Graumann , M. Fattouche An FPGA implementation of a matched filter detector for spread spectrum communications systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sayan Teerapnyawatt , Krit Athikulwongse An NTSC and PAL closed caption processor. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Kean , Ann Duncan A 800 Mpixel/sec reconfigurable image correlator on XC6216. [Citation Graph (0, 0)][DBLP ] Conf ] Ferran Lisa , Faustino Cuadrado , Dolores Rexachs , Jordi Carrabina A reconfigurable coprocessor for a PCI-based real time computer vision system. [Citation Graph (0, 0)][DBLP ] Conf ] Paul A. Dunn , Peter I. Corke Real-time stereopsis using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] C. C. Jong , Y. Y. H. Lam , L. S. Ng FPGA implementation of a digital IQ demodulator using VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Ian Page Hardware compilation, configurable platforms and ASICs for self-validating sensors. [Citation Graph (0, 0)][DBLP ] Conf ] Satnam Singh , John W. Patterson , Jim Burns , Michael Dales PostscriptTM rendering with virtual hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Ilija Hadzic , Jonathan M. Smith P4: A platform for FPGA implementation of protocol boosters. [Citation Graph (0, 0)][DBLP ] Conf ] Miron Abramovici , Daniel G. Saab Satisfiability on reconfigurable hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Tudor Jebelean Auto-configurable array for GCD computation. [Citation Graph (0, 0)][DBLP ] Conf ] Bernard Laurent , G. Bosco , Gabriele Saucier Structural versus algorithmic approaches for efficient adders on Xilinx 5200 FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaud Tisserand , Martin Dimmler FPGA implementation of real-time digital controllers using on-line arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Hollstein , Andreas Kirschbaum , Manfred Glesner A prototyping environment for fuzzy controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Kazumasa Nukata , Yuichiro Shibata , Hideharu Amano , Yuichiro Anzai A reconfigurable sensor-data processing system for personal robots. [Citation Graph (0, 0)][DBLP ] Conf ] 