Conferences in DBLP
Paul Graham , Brent E. Nelson Reconfigurable Processors for High-Performance, Embedded Digital Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Brucke , Arne Schulz , Wolfgang Nebel Auditory Signal Processing in Hardware: A Linear Gammatone Filterbank Design for a Model of the Auditory System. [Citation Graph (0, 0)][DBLP ] Conf ] Simon D. Haynes , Peter Y. K. Cheung , Wayne Luk , John Stone SONIC - A Plug-In Architecture for Video Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Kiran Bondalapati , Viktor K. Prasanna DRIVE: An Interpretive Simulation and Visualization Environment for Dynamically Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] David Robinson , Patrick Lysaght Modelling and Synthesis of Configuration Controllers for Dynamically Reconfigurable Logic Systems Using the DCS CAD Framework. [Citation Graph (0, 0)][DBLP ] Conf ] Gregory C. Ahlquist , Brent E. Nelson , Michael Rice Optimal Finite Field Multipliers for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Markus Weinhardt , Wayne Luk Memory Access Optimization and RAM Inference for Pipeline Vectorization. [Citation Graph (0, 0)][DBLP ] Conf ] Silviu M. S. A. Chiricescu , Mankuan Michael Vai Analysis and Optimization of 3-D FPGA Design Parameters. [Citation Graph (0, 0)][DBLP ] Conf ] John M. Emmert , Dinesh Bhatia Tabu Search: Ultra-Fast Placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Juan de Vicente , Juan Lanchares , Román Hermida Placement Optimization Based on Global Routing Updating for System Partitioning onto Multi-FPGA Mesh Topologies. [Citation Graph (0, 0)][DBLP ] Conf ] Helena Krupnova , Gabriele Saucier Hierarchical Interactive Approach to Partition Large Designs into FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] William K. C. Ho , Steven J. E. Wilton Logical-to-Physical Memory Mapping for FPGAs with Dual-Port Embedded Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Milan Vasilko DYNASTY: A Temporal Floorplanning Based CAD Framework for Dynamically Reconfigurable Logic Systems. [Citation Graph (0, 0)][DBLP ] Conf ] E. Cantó , Juan Manuel Moreno , Joan Cabestany , Julio Faura , Josep Maria Insenser A Bipartitioning Algorithm for Dynamic Reconfigurable Programmable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon McGregor , Patrick Lysaght Self Controlling Dynamic Reconfiguration: A Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Michael Herz , Ulrich Nageldinger , Thomas Hoffmann An Internet Based Development Framework for Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Koch On Tool Integration in High-Performance FPGA Design Flows. [Citation Graph (0, 0)][DBLP ] Conf ] Karam S. Chatha , Ranga Vemuri Hardware-Software Codesign for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Wayne Luk , Arran Derbyshire , Shaori Guo , D. Siganos Serial Hardware Libraries for Reconfigurable Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner , Neil W. Bergmann Reconfigurable Computing in Remote and Harsh Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Eisenring , Marco Platzner , Lothar Thiele Communication Synthesis for Reconfigurable Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Guccione , Delon Levi Run-Time Parameterizable Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Donald MacVicar , John W. Patterson , Satnam Singh Rendering Postscript Fonts on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan H.-M. Ludwig , Robert Slous , Satnam Singh Implementing Photoshop Filters in Virtex. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Feske , Michael Scholz , Günther Döring , Denis Nareike Rapid FPGA Prototyping of a DAB Test Data Generator Using Protocol Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Nabeel Shirazi , Wayne Luk , Dan Benyamin , Peter Y. K. Cheung Quantitative Analysis of Run-Time Reconfigurable Database Search. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaud Tisserand , Pierre Marchal , Christian Piguet An On-Line Arithmetic Based FPGA for Low-Power Custom Computing. [Citation Graph (0, 0)][DBLP ] Conf ] M. Imran Masud , Steven J. E. Wilton A New Switch Block for Segmented FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Gareth Jones PulseDSP - A Signal Processing Oriented Programmable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Ilija Hadzic , Sanjay Udani , Jonathan M. Smith FPGA Viruses. [Citation Graph (0, 0)][DBLP ] Conf ] Reetinder P. S. Sidhu , Alessandro Mei , Viktor K. Prasanna Genetic Programming Using Self-Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Arnaldo Oliveira , Andreia Melo , Valery Sklyarov Specification, Implementation and Testing of HFSMs in Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] George A. Constantinides , Peter Y. K. Cheung , Wayne Luk Synthia : Synthesis of Interacting Automata Targeting LUT-based FPGAs.Citation Graph (0, 0)][DBLP ] Conf ] Holger Kropp , Carsten Reuter , Matthias Wiege , Tien-Toan Do , Peter Pirsch An FPGA-based Prototyping System for Real-Time Verification of Video Processing Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Tomas Dulik An FPGA Implementation of Goertzel Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Mathew Wojko Pipelined Multipliers and FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Emanuel M. Popovici , Patrick Fitzpatrick , Colin C. Murphy FPGA Design Trade-Offs for Solving the Key Equation in Reed-Solomon Decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Juri Põldre , Kalle Tammemäe Reconfigurable Multiplier for Virtex FPGA Family. [Citation Graph (0, 0)][DBLP ] Conf ] Iakovos Stamoulis , Martin White , Paul F. Lister Pipelined Floating Point Arithmetic Optimized for FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel Holmström SL - A Structural Hardware Design Language. [Citation Graph (0, 0)][DBLP ] Conf ] R. Bruce Maunder , Zoran A. Salcic , George G. Coghill High-Level Hierachical HDL Synthesis of Pipelined FPGA-Based Circuits Using Synchronous Modules. [Citation Graph (0, 0)][DBLP ] Conf ] Reiner W. Hartenstein , Michael Herz , Thomas Hoffmann , Ulrich Nageldinger Mapping Applications onto Reconfigurable Kress Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Danek , Zdenek Muzikár Global Routing Models. [Citation Graph (0, 0)][DBLP ] Conf ] Andrés D. García , Wayne P. Burleson , Jean-Luc Danger Power Modelling in Field Programmable Gate Arrays (FPGA). [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh Bhatia , Kuldeep S. Simha , PariVallal Kannan NEBULA: A Partially and Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Keith J. Symington , John F. Snowdon , Heiko Schroeder High Bandwidth Dynamically Reconfigurable Architectures Using Optical Interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Torsten Kuberka , Andreas Kugel , Reinhard Männer , Holger Singpiel , R. Spurzem , R. Klessen AHA-GRAPE: Adaptive Hydrodynamic Architecture-GRAvity PipE. [Citation Graph (0, 0)][DBLP ] Conf ] Malachy Devlin , Allan J. Cantle DIME - The First Module Standard for FPGA Based High Performance Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Dales The Proteus Processor - A Conventional CPU with Reconfigurable Functionality. [Citation Graph (0, 0)][DBLP ] Conf ] Valeri F. Tomashau Logic Circuit Speeding up through Multiplexing. [Citation Graph (0, 0)][DBLP ] Conf ] Philip James-Roxby , Elena Cerro-Prada A Wildcarding Mechanism for Acceleration of Partial Configurations. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Maruyama , Masaaki Takagi , Tsutomu Hoshino Hardware Implementation Techniques for Recursive Calls and Loops. [Citation Graph (0, 0)][DBLP ] Conf ] Juanjo Noguera , Rosa M. Badia , Jordi Domingo-Pascual , Josep Solé-Pareta A HW/SW Codesign-Based Reconfigurable Environment for Telecommunication Network Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] María Dolores Valdés , María José Moure , Enrique Mandado , Angel Salaverría An Alternative Solution for Reconfigurable Coprocessors Hardware and Interface Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Abdellah Touhafi , Wouter Brissinck , Erik F. Dirkx Reconfigurable Programming in the Large on Extendable Uniform Reconfigurable Computing Array's: An Integrated Approach Based on Reconfigurable Virtual Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Sergej Sawitzki , Rainer G. Spallek A Concept for an Evaluation Framework for Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Rainer Kress , Andreas Pyttel Debugging Application-Specific Programmable Products. [Citation Graph (0, 0)][DBLP ] Conf ] Steve Casselman , John Schewel , Christophe Beaumont IP Validation for FPGAs Using Hardware Object Technology. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Böge , Andreas Koch A Processor for Artificial Life Simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Craig Slorach , Steve Fulton , Ken Sharman A Distributed, Scalable, Multi-layered Approach to Evolvable System Design Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tri Caohuu , Thuy Trong Le , Manfred Glesner , Jürgen Becker Dynamically Reconfigurable Reduced Crossbar: A Novel Approach to Large Scale Switching. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Maruyama , Tsutomu Hoshino A Reconfigurable Architecture for High Speed Computation by Pipeline Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Bernardo Kastrup , Jef L. van Meerbergen , Katarzyna Nowak Seeking (the right) Problems for the Solutions of Reconfigurable Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Wong Hiu Yung , Wing Seung Yuen , Kin-Hong Lee , Philip Heng Wai Leong A Runtime Reconfigurable Implementation of the GSAT Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Kolja Sulimma , Dominik Stoffel , Wolfgang Kunz Accelerating Boolean Implications with FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] 