Conferences in DBLP
Michael J. Flynn , Albert A. Liddicoat Technology Trends and Adaptive Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Sergej Sawitzki , Steffen Köhler , Rainer G. Spallek Prototyping Framework for Reconfigurable Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Fisher , Kevin Rennie , Guanbin Xing , Stefan G. Berg , Kevin Bolding , John H. Naegle , Daniel Parshall , Dmitriy Portnov , Adnan Sulejmanpasic , Carl Ebeling An Emulator for Exploring RaPiD Configurable Computing Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Joerg Abke , Erich Barke A New Placement Method for Direct Mapping into LUT-Based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] PariVallal Kannan , Shankar Balachandran , Dinesh Bhatia fGREP - Fast Generic Routing Demand Estimation for Placed FPGA Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ernie Lin , Steven J. E. Wilton Macrocell Architectures for Product Term Embedded Memory Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Bryan S. Goda , Russell P. Kraft , Steven R. Carlough , Thomas W. Krawczyk Jr. , John F. McDonald Gigahertz Reconfigurable Computing Using SiGe HBT BiCMOS FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Kasat , Iyad Ouaiss , Ranga Vemuri Memory Synthesis for FPGA-Based Reconfigurable Computers. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Melnikoff , Steven F. Quigley , Martin J. Russell Implementing a Hidden Markov Model Speech Recognition System in Programmable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Felix Albu , Jiri Kadlec , Chris Softley , Rudolf Matousek , Antonin Hermanek , Nick Coleman , Anthony Fagan Implementation of (Normalised) RLS Lattice on Virtex. [Citation Graph (0, 0)][DBLP ] Conf ] Abbes Amira , Ahmed Bouridane , Peter Milligan Accelerating Matrix Product on Reconfigurable Hardware for Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Srihari Cadambi , Seth Copen Goldstein Static Profile-Driven Compilation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Wirthlin , Brad L. Hutchings , Carl Worth Synthesizing RTL Hardware from Java Byte Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Harbich , Erich Barke PuMA++: From Behavioral Specification to Multi-FPGA-Prototype. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Kean Secure Configuration of Field Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Máire McLoone , John V. McCanny Single-Chip FPGA Implementation of the Advanced Encryption Standard Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Scott McMillan , Cameron Patterson JBitsTM Implementations of the Advanced Encryption Standard (Rijndael). [Citation Graph (0, 0)][DBLP ] Conf ] Markus Weinhardt , Wayne Luk Task-Parallel Programming of Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner , Oliver Diessel Chip-Based Reconfigurable Task Management. [Citation Graph (0, 0)][DBLP ] Conf ] Suraj Sudhir , Suman Nath , Seth Copen Goldstein Configuration Caching and Swapping. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Arias-Estrada , Juan M. Xicotencatl Multiple Stereo Matching Using an Extended Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Paula N. Mallón , Montserrat Bóo , Javier D. Bruguera Implementation of a NURBS to Bézier Conversor with Constant Latency. [Citation Graph (0, 0)][DBLP ] Conf ] Sergio A. Cuenca , Francisco Ibarra , Rafael Alvarez Reconfigurable Frame-Grabber for Real-Time Automated Visual Inspection (RT-AVI) Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jeff Lawrence Processing Models for the Next Generation Network [Abstract]. [Citation Graph (0, 0)][DBLP ] Conf ] PariVallal Kannan , Dinesh Bhatia Tightly Integrated Placement and Routing for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] John Karro , James P. Cohoon Gambit: A Tool for the Simultaneous Placement and Detailed Routing of Gate-Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Braun , John W. Lockwood , Marcel Waldvogel Reconfigurable Router Modules Using Network Protocol Wrappers. [Citation Graph (0, 0)][DBLP ] Conf ] Yajun Ha , Bingfeng Mei , Patrick Schaumont , Serge Vernalde , Rudy Lauwereins , Hugo De Man Development of a Design Framework for Platform-Independent Networked Reconfiguration of Software and Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Stamatis Vassiliadis , Stephan Wong , Sorin Cotofana The MOLEN rho-mu-Coded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Marios Iliopoulos , Theodore Antonakopoulos Run-Time Optimized Reconfiguration Using Instruction Forecasting. [Citation Graph (0, 0)][DBLP ] Conf ] Pieter Op de Beeck , Francisco Barat , Murali Jayapala , Rudy Lauwereins CRISP: A Template for Reconfigurable Instruction Set Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin Carrión Schäfer , Steven F. Quigley , Andrew H. C. Chan Evaluation of an FPGA Implementation of the Discrete Element Method. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Dandalis , Viktor K. Prasanna , Bharani Thiruvengadam Run-Time Performance Optimization of an FPGA-Based Deduction Engine for SAT Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Apostolos Dollas , Kyprianos Papademetriou , Nikolaos Aslanides , Tom Kean A Reconfigurable Embedded Input Device for Kinetically Challenged Persons. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Wolz , Reiner Kolla Bubble Partitioning for LUT-Based Sequential Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Satnam Singh , Philip James-Roxby Rapid Construction of Partial Configuration Datastreams from High-Level Constructs Using JBits. [Citation Graph (0, 0)][DBLP ] Conf ] Loïc Lagadec , Dominique Lavenier , Erwan Fabiani , Bernard Pottier Placing, Routing, and Editing Virtual FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Lok-Kee Ting , Roger Woods , Colin Cowan Virtex Implementation of Pipelined Adaptive LMS Predictor in Electronic Support Measures Receiver. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Saito , Tsutomu Maruyama , Tsutomu Hoshino , Saburo Hirano A Music Synthesizer on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Shervin Sheidaei , Hamid Noori , Ahmad Akbari , Hossein Pedram Motivation from a Full-Rate Specific Design to a DSP Core Approach for GSM Vocoders. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Derrien , Sanjay V. Rajopadhye Loop Tiling for Reconfigurable Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Gilles Sassatelli , Lionel Torres , Jérôme Galy , Gaston Cambon , Camille Diou The Systolic Ring: A Dynamically Reconfigurable Architecture for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Oswaldo Cadenas , Graham M. Megson A n-Bit Reconfigurable Scalar Quantiser. [Citation Graph (0, 0)][DBLP ] Conf ] Jerzy Kasperek Real Time Morphological Image Contrast Enhancement in Virtex FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Albert Simpson , Jill Hunter , Moira Wylie , Yi Hu , David Mann Demonstrating Real-Time JPEG Image Compression-Decompression Using Standard Component IP Cores on a Programmable Logic Based Platform for DSP and Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Nikolaus Voß , Bärbel Mertsching Design and Implementation of an Accelerated Gabor Filter Bank Using Parallel Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Bill Carter The Evolution of Programmable Logic: Past, Present, and Future Predictions [Abstract]. [Citation Graph (0, 0)][DBLP ] Conf ] John MacBeth , Patrick Lysaght Dynamically Reconfigurable Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Price , Cameron Patterson Reconfigurable Breakpoints for Co-debug. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Wheeler , Paul Graham , Brent E. Nelson , Brad L. Hutchings Using Design-Level Scan to Improve FPGA Design Observability and Controllability for Functional Verification. [Citation Graph (0, 0)][DBLP ] Conf ] Pierluigi Civera , Luca Macchiarulo , Maurizio Rebaudengo , Matteo Sonza Reorda , Massimo Violante FPGA-Based Fault Injection Techniques for Fast Evaluation of Fault Tolerance in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Tilman Neumann , Andreas Koch A Generic Library for Adaptive Computing Environments. [Citation Graph (0, 0)][DBLP ] Conf ] Stephan Rühl , Peter Dillinger , Stefan Hezel , Reinhard Männer Generative Development System for FPGA Processors with Active Components. [Citation Graph (0, 0)][DBLP ] Conf ] João M. P. Cardoso , Horácio C. Neto Compilation Increasing the Scheduling Scope for Multi-memory-FPGA-Based Custom Computing Machines. [Citation Graph (0, 0)][DBLP ] Conf ] James Hwang , Brent Milne , Nabeel Shirazi , Jeffrey D. Stroomer System Level Tools for DSP in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Oskar Mencer , Nicolas Boullis , Wayne Luk , Henry Styles Parameterized Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Wirthlin , Brian McMurtrey Efficient Constant Coefficient Multiplication Using Advanced FPGA Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Chakkapas Visavakul , Peter Y. K. Cheung , Wayne Luk A Digit-Serial Structure for Reconfigurable Multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Kent E. Wires , Michael J. Schulte , Don McCarley FPGA Resource Reduction Through Truncated Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Jürgen Becker , Nicolas Liebau , Thilo Pionteck , Manfred Glesner Efficient Mapping of Pre-synthesized IP-Cores onto Dynamically Reconfigurable Array Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Cristian Ciressan , Eduardo Sanchez , Martin Rajman , Jean-Cédric Chappelier An FPGA-Based Syntactic Parser for Real-Life Almost Unrestricted Context-Free Grammars. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Harkin , T. Martin McGinnity , Liam P. Maguire Hardware-Software Partitioning: A Reconfigurable and Evolutionary Computing Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Maruyama , Yoshiki Yamaguchi , Atsushi Kawase An Approach to Real-Time Visualization of PIV Method with FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Mokhtar Nibouche , Ahmed Bouridane , Fionn Murtagh , Omar Nibouche FPGA-Based Discrete Wavelet Transforms System. [Citation Graph (0, 0)][DBLP ] Conf ] Jose Luis Nunez , Claudia Feregrino , Simon Jones , Stephen Bateman X-MatchPRO: A ProASIC-Based 200 Mbytes/s Full-Duplex Lossless Data Compressor. [Citation Graph (0, 0)][DBLP ] Conf ] Tsukasa Yamauchi , Shogo Nakaya , Takeshi Inuo , Nobuki Kajihara Arithmetic Operation Oriented Reconfigurable Chip: RHW. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Dales Initial Analysis of the Proteus Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Keller Building Asynchronous Circuits with JBits. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Lehmann , Andreas Schreckenberg Case Study of Integration of Reconfigurable Logic as a Coprocessor into a SCI-Cluster under RT-Linux. [Citation Graph (0, 0)][DBLP ] Conf ] Raymond Sinnappan , Scott Hazelhurst A Reconfigurable Approach to Packet Filtering. [Citation Graph (0, 0)][DBLP ] Conf ] Riad Stefo , Jose Luis Nunez , Claudia Feregrino , Sudipta Mahapatra , Simon Jones FPGA-Based Modelling Unit for High Speed Lossless Arithmetic Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Ram Subramanian , Santosh Pande A Data Re-use Based Compiler Optimization for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Matti Tommiska , Jorma Skyttä Dijkstra's Shortest Path Routing Algorithm in Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Isidoro Urriza , José I. García-Nicolás , Alfredo Sanz , Antonio Valdovinos A System on Chip for Power Line Communications According to European Home Systems Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] 