Conferences in DBLP
Robert G. Dimond , Oskar Mencer , Wayne Luk CUSTARD - A Customisable Threaded FPGA Soft Processor and Tools. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiguo Ge , Hock-Beng Lim , Weng-Fai Wong A Reconfigurable Instruction Memory Hierarchy for Embedded Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Lanuzza , Stefania Perri , Martin Margala , Pasquale Corsonello Low-Cost Fully Reconfigurable Data-Path for FPGA-Based Multimedia Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew C. Ling , Deshanand P. Singh , Stephen Dean Brown FPGA PLB Evaluation using Quantified Boolean Satisfiability. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Morra , Jürgen Becker , Mauricio Ayala-Rincón , Reiner W. Hartenstein FELIX: Using Rewriting-Logic for Generating Functionally Equivalent Implementations. [Citation Graph (0, 0)][DBLP ] Conf ] Valavan Manohararajah , Deshanand P. Singh , Stephen Dean Brown Post-Placement BDD-Based Decomposition for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Giorgos Papadopoulos , Dionisios N. Pnevmatikatos Hashing + Memory = Low Cost, Exact Pattern Matching. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Sugawara , Mary Inaba , Kei Hiraki High-speed and Memory Efficient TCP Stream Scanning using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Todd S. Sproull , Gordon J. Brebner , Christopher E. Neely Mutable Codesign for Embedded Protocol Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Wei Wang , Nicholas P. Carter , Richard B. Kujoth , Jeffrey J. Cook , Derek B. Gottlieb Exploiting Pipelining to Tolerate Wire Delays in a Programmable-Reconfigurable Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Hisashi Tsukiashi , Masahiro Iida , Toshinori Sueyoshi Applying the Small-World Network to Routing Structure of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Michael B. Healy , Mongkol Ekpanyapong , Sung Kyu Lim MILP-based Placement and Routing for Dataflow Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Gareth W. Morris , George A. Constantinides , Peter Y. K. Cheung Using DSP Blocks For ROM Replacement: A Novel Synthesis Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Kenji Kanazawa , Tsutomu Maruyama An FPGA Solver for WSAT Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Domingos , Fernando M. Silva , Horácio C. Neto An Efficient and Scalable Architecture for Neural Networks with Backpropagation Learning. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Holland , Scott Hauck Automatic Creation of Domain-Specific Reconfigurable CPLDs for SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Chao You , Jong-Ru Guo , Michael Chu , Russell P. Kraft , Bryan S. Goda , John F. McDonald A 11 GHz FPGA with Test Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco-Javier Veredas , Michael Scheppler , Will Moffat , Bingfeng Mei Custom Implementation of the Coarse-Grained Reconfigurable ADRES Architecture for Multimedia Purposes. [Citation Graph (0, 0)][DBLP ] Conf ] Nalin Sidahao , George A. Constantinides , Peter Y. K. Cheung Power and Area Optimization for Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Sasao , Shinobu Nagayama , Jon T. Butler Programmable Numerical Function Generators: Architectures and Synthesis Method. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Te Ewe , Peter Y. K. Cheung , George A. Constantinides Error Modelling of Dual FiXed-point Arithmetic and its Application in Field Programmable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Marek Gorgon , Slawomir Cichon , Miroslaw Pac Real-time Handel-C Based Implementation of DV Decoder. [Citation Graph (0, 0)][DBLP ] Conf ] Najeem Lawal , Benny Thörnberg , Mattias O'Nils Address Generation for FPGA RAMs for Efficient Implementation of Real-Time Video Processing Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Suhaib A. Fahmy , Peter Y. K. Cheung , Wayne Luk Novel FPGA-Based Implementation of Median and Weighted Median Filters for Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] John Esquiagola , Guilherme Ozari , Marcio Yukio Teruya , Marius Strum , Wang Jiang Chau A Dynamically Reconfigurable Bluetooth Base Band Unit. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Bobda , Ali Ahmadinia , Mateusz Majer , Jürgen Teich , Sándor P. Fekete , Jan van der Veen DyNoC: A Dynamic Infrastructure for Communication in Dynamically Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Andy Gean Ye , Jonathan Rose Measuring and Utilizing the Correlation Between Signal Connectivity and Signal Positioning for FPGAs Containing Multi-Bit Building Blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Shankar Balachandran , Dinesh Bhatia Timing Aware Interconnect Prediction Models for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Shingo Masuno , Tsutomu Maruyama , Yoshiki Yamaguchi , Akihiko Konagaya Multidimensional Dynamic Programming for Homology Search. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Niitsuma , Tsutomu Maruyama Real-time Generation of Three-Dimensional Motion Fields. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Oppold , Thomas Schweizer , Tommy Kuhn , Wolfgang Rosenstiel , Urs Kanus , Wolfgang Straßer Evaluation of Ray Casting on Processor-Like Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Clint Hilton , Brent E. Nelson A Flexible Circuit-Switched NOC for FPGA-Based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal T. Wolkotte , Gerard J. M. Smit , Jens E. Becker Energy-Efficient NoC for Best-Effort Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Heikki Kariniemi , Jari Nurmi Fault-Tolerant XGFT Network-On-Chip for Multi-Processor System-on-Chip Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] N. Pete Sedcole , Brandon Blodget , Tobias Becker , James Anderson , Patrick Lysaght Modular Partial Reconfiguration in Virtex FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Nico Kasprzyk , Jan van der Veen , Andreas Koch Configuration Merging for Adaptive Computer Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Heiko Kalte , Mario Porrmann Context Saving and Restoring for Multitasking in Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dusan Suvakovic , Ilija Hadzic An FPGA Application with High Speed Serial Transceiver Running at Sub-nominal Rate. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Iouliia Skliarova , Bruno S. Pimentel FPGA-based implementation and comparison of recursive and iterative algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Marc Bautista-Palacios , Luis Baldez , Jordi Sempere-Agulló , Atilà Herms-Berenguer , Francisco Cardells-Tormo , Pep-Lluis Molinet Configurable Hardware/Software Architecture for Data Acquisition: Implementation on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Zohair Hyder , John Wawrzynek Defect Tolerance in Multiple-FPGA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony J. Yu , Guy G. Lemieux Defect-Tolerant FPGA Switch Block and Connection Block with Fine-Grain Redundancy for Yield Enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Christos-Savvas Bouganis , Peter Y. K. Cheung , George A. Constantinides Heterogeneity Exploration for Multiple 2D Filter Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Seppo Virtanen , Dragos Truscan , Jani Paakkulainen , Jouni Isoaho , Johan Lilius Highly Automated FPGA Synthesis of Application-Specific Protocol Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Guanglie Zhang , Philip Heng Wai Leong , Dong-U Lee , John D. Villasenor , Ray C. C. Cheung , Wayne Luk Ziggurat-based Hardware Gaussian Random Number Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Wenhai Fang , Thomas Johansson , Lambert Spaanenburg Snow 2.0 IP Core for Trusted Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Jia , Ranga Vemuri A Novel Asynchronous FPGA Architecture Design and Its Performance Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Laurent Fesquet , Marc Renaudin A Programmable Logic Architecture for Prototyping Clockless Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jerome Quartana , Salim Renane , Arnaud Baixas , Laurent Fesquet , Marc Renaudin GALS systems prototyping using multiclock FPGAs and asynchronous network-on-chips. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Jamieson , Jonathan Rose A Verilog RTL Synthesis Tool for Heterogeneous FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Henry Styles , Wayne Luk Compilation and Management of Phase-Optimized Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Justin L. Tripp , Kristopher D. Peterson , Christine Ahrens , Jeffrey D. Poznanovic , Maya Gokhale Trident: An FPGA Compiler Framework for Floating-Point Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Iosifina Pournara , Christos-Savvas Bouganis , George A. Constantinides FPGA-Accelerated Reconstruction of Gene Regulatory Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zipf , Oliver Soffke , Andre Schumacher , Radu Dogaru , Manfred Glesner Programmable and Reconfigurable Hardware Architectures for the Rapid Prototyping of Cellular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Zipf , Oliver Soffke , Andre Schumacher , Clemens Schlachta , Radu Dogaru , Manfred Glesner A Hardware-in-the-Loop System to Evaluate the Performance of Small-World Cellular Automata. [Citation Graph (0, 0)][DBLP ] Conf ] Alastair M. Smith , George A. Constantinides , Peter Y. K. Cheung An Analytical Approach to Generation and Exploration of Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Shohei Abe , Katsuaki Deguchi , Yohei Hasegawa An I/O mechanism on a Dynamically Reconfigurable Processor - Which should be moved: Data or Configuration? [Citation Graph (0, 0)][DBLP ] Conf ] Miyoshi Saito , Hisanori Fujisawa , Nobuo Ujiie , Hideki Yoshizawa Cluster Architecture for Reconfigurable Signal Processing Engine for Wireless Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Claudiu Zissulescu , Bart Kienhuis , Ed F. Deprettere Communication Synthesis in a multiprocessor environment. [Citation Graph (0, 0)][DBLP ] Conf ] Tsuyoshi Hamada , Naohito Nakasato PGR: A Software Package for Reconfigurable Super-Computing. [Citation Graph (0, 0)][DBLP ] Conf ] Sujan Pandey , Manfred Glesner , Max Mühlhäuser On-Chip Communication Topology Synthesis for a Shared Memory Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Olli Lehtoranta , Erno Salminen , Ari Kulmala , Marko Hännikäinen , Timo D. Hämäläinen A Parallel MPEG-4 Encoder for FPGA Based Multiprocessor SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Janiaut , Camel Tanougast , Hassan Rabah , Yves Berviller , Christian Mannino , Serge Weber Configurable hardware implementation of a conceptual decoder for a real-time MPEG-2 analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Kristof Denolf , Adrian Chirila-Rus , Robert D. Turney , Paul R. Schumacher , Kees A. Vissers Memory Efficient Design of an MPEG-4 Video Encoder for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Celia López-Ongil , Mario García-Valderas , Marta Portela-García , Luis Entrena-Arrontes An Autonomous FPGA-based Emulation System for Fast Fault Tolerant Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Olivier Héron , Talal Arnaout , Hans-Joachim Wunderlich On the Reliability Evaluation of SRAM-Based FPGA Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Campregher , Peter Y. K. Cheung , George A. Constantinides , Milan Vasilko Yield modelling and Yield Enhancement for FPGAs using Fault Tolerance Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Pritha Banerjee , Subhasis Bhattacharjee , Susmita Sur-Kolay , Sandip Das , Subhas C. Nandy Fast FPGA Placement using Space-filling Curve. [Citation Graph (0, 0)][DBLP ] Conf ] I. Faik Baskaya , Sasank Reddy , Sung Kyu Lim , David V. Anderson Hierarchical Placement for Large-scale FPAA. [Citation Graph (0, 0)][DBLP ] Conf ] Akshay Sharma , Carl Ebeling , Scott Hauck Architecture-Adaptive Routability-Driven Placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Vincent Carlier , Hervé Chabanne , Emmanuelle Dottax , Hervé Pelletier Generalizing Square Attack using Side-Channels of an AES Implementation on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] David Nguyen , Gokhan Memik , Seda Ogrenci Memik , Alok N. Choudhary Real-Time Feature Extraction for High Speed Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Sherif Yusuf , Wayne Luk Bitwise Optimised CAM for Network Intrusion Detection Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Shrutisagar Chandrasekaran , Abbes Amira High Speed / Low Power Architectures for the Finite Radon Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastien Wong , Mark Jasiunas , David A. Kearney Towards a Reconfigurable Tracking System. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Díaz , Eduardo Ros , Sonia Mota , Eva M. Ortigosa , Begoña del Pino High Performance Stereo Computation Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Qiang Qiang , Daniel G. Saab , Jacob A. Abraham An Emulation Model for Sequential ATPG-Based Bounded Model Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Yongfeng Gu , Tom Van Court , Martin C. Herbordt Accelerating Molecular Dynamics Simulations With Configurable Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Gonçalves , José T. de Sousa , Fernando M. Gonçalves A Low-Cost Scalable Pipelined Reconfigurable Architecture for Simulation of Digital Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik Ravindran , Nadathur Satish , Yujia Jin , Kurt Keutzer An FPGA-based Soft Multiprocessor System for IPv4 Packet Forwarding. [Citation Graph (0, 0)][DBLP ] Conf ] Haoyu Song , Todd S. Sproull , Michael Attig , John W. Lockwood Snort Offloader: A Reconfigurable Hardware NIDS Filter. [Citation Graph (0, 0)][DBLP ] Conf ] Charles M. Kastner , G. Adam Covington , Andrew A. Levine , John W. Lockwood HAIL: A Hardware-Accelerated Algorithm for Language Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Rawat Siripokarpirom A Run-Time Reconfigurable Hardware Infrastructure for IP-Core Evaluation and Test. [Citation Graph (0, 0)][DBLP ] Conf ] Sinan Yalcin , Hasan F. Ates , Ilker Hamzaoglu A High Performance Hardware Architecture for an SAD Reuse based Hierarchical Motion Estimation Algorithm for H.264 Video Coding. [Citation Graph (0, 0)][DBLP ] Conf ] Elias Todorovich , F. Angarita , J. Valls , Eduardo I. Boemo Statistical Power Estimation for FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Georg Acher , Rainer Buchty , Carsten Trinitis CPU-independent Assembler in an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] C. Leong , P. Bento , P. Rodrigues , A. Trindade , J. C. Silva , P. Lousã , J. Rego , J. Nobre , J. Varela , João Paulo Teixeira , Isabel C. Teixeira Design and Test Methodology for a Reconfigurable PEM Data Acquisition Electronics System. [Citation Graph (0, 0)][DBLP ] Conf ] Ronald Hecht , Stephan Kubisch , Andreas Herrholtz , Dirk Timmermann Dynamic Reconfiguration with hardwired Networks-on-Chip on future FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Antonio García , Javier Ramírez , Uwe Meyer-Bäse , Encarnación Castillo , Antonio Lloris-Ruíz Efficient Embedded FPL Resource Usage for RNS-based Polyphase DWT Filter Banks. [Citation Graph (0, 0)][DBLP ] Conf ] F. Angarita , A. Perez-Pascual , T. Sansaloni , J. Valls Efficient FPGA Implementation of CORDIC Algorithm for Circular and Linear Coordinates. [Citation Graph (0, 0)][DBLP ] Conf ] David Narh Amanor , Viktor Bunimov , Christof Paar , Jan Pelzl , Manfred Schimmler Efficient Hardware Architectures for Modular Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jawad Khan , Ranga Vemuri Energy Management in Battery-Powered Sensor Networks with Reconfigurable Computing Nodes. [Citation Graph (0, 0)][DBLP ] Conf ] J. Javier Martínez , F. Javier Toledo , F. Javier Garrigós , José Manuel Ferrández FPGA Implementation of an Area-Time Efficient FIR Filter Core Using a Self-Clocked Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Artur Schiefer , Udo Kebschull Optimization of Start-Up Time and Quiescent Power Consumption of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Yonghong Xu , Mohammed A. S. Khalid QPF: Efficient Quadratic Placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jacobo Alvarez , Jorge Marcos , Santiago Fernandez Safe PLD-based Programmable Controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Juanjo Noguera , Rosa M. Badia Performance and Energy Analysis of Task-Level Graph Transformation Techniques for Dynamically Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Danne , Marco Platzner A Heuristic Approach to Schedule Periodic Real-Time Tasks on Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Yasunori Osana , Yow Iwaoka , Tomonori Fukushima , Masato Yoshimi , Akira Funahashi , Noriko Hiroi , Yuichiro Shibata , Naoki Iwanaga , Hiroaki Kitano , Hideharu Amano A Framework for ODE-Based Multimodel Biochemical Simulations on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco Cardells-Tormo , Pep-Lluis Molinet , Jordi Sempere-Agulló , Luis Baldez , Marc Bautista-Palacios Area-Efficient 2-D Shift-Variant Convolvers for FPGA-based Digital Image Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Pearson , Chris Melhuish , Anthony G. Pipe , Mokhtar Nibouche , Ian Gilhespy , Kevin N. Gurney , Benjamin Mitchinson Design and FPGA Implementation of an Embedded Real-Time Biologically Plausible Spiking Neural Network Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Hendrik Lange , Hartmut Schröder Evaluation Strategies for Coarse Grained Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kelly Nasi , Martin Danek , Theodoros Karoubalis , Zdenek Pohl Figaro - An Automatic Tool Flow for Designs with Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Maurice Keller , Tim Kerins , William P. Marnane FPGA Implementation of a GF(24M ) Multiplier for use in Pairing Based Cryptosystems. [Citation Graph (0, 0)][DBLP ] Conf ] Xavier Revés , Vuk Marojevic , Ramon Ferrús , Antoni Gelonch FPGA's Middleware for Software Defined Radio Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Dragomir Milojevic Implementation of Ranking Filters on General Purpose and Reconfigurable Architecture Based on High Density FPGA Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Tapani Ahonen , Jari Nurmi Integration of a NoC-Based Multimedia Processing Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Martin C. Herbordt LAMP: A Tool Suite for Families of FPGA-Based Application Accelerators. [Citation Graph (0, 0)][DBLP ] Conf ] Sajid Baloch , Imran Ahmed , Tughrul Arslan , Adrian Stoica Low Power Domain-Specific Reconfigurable Array for Discrete Wavelet Transforms Targeting Multimedia Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Bingfeng Mei , Francisco-Javier Veredas , Bart Masschelein Mapping an H.264/AVC Decoder onto the ADRES Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan A. Clarke , Altaf Abdul Gaffar , George A. Constantinides Parameterized Logic Power Consumption Models for FPGA based Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Grigoris Dimitroulakos , Michalis D. Galanis , Costas E. Goutis Performance Improvements using Coarse-Grain Reconfigurable Logic in Embedded SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Usama Malik , Oliver Diessel A Configuration Memory Architecture for Fast Run-Time-Reconfiguration of FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Danilin , Martijn T. Bennebroek , Sergei Sawitzki A Novel Toolset for the Development of FPGA-like Reconfigurable Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Ioannis Sourdis , Dionisios N. Pnevmatikatos , Stephan Wong , Stamatis Vassiliadis A Reconfigurable Perfect-Hashing Scheme for Packet Inspection. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Qu , Juha-Pekka Soininen , Jari Nurmi An Efficient Approach to Hide the Run-Time Reconfiguration from SW Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chin Mun Wee , Peter R. Sutton , Neil W. Bergmann An FPGA Network Architecture for Accelerating 3DES - CBC. [Citation Graph (0, 0)][DBLP ] Conf ] K. Siozios , Konstantinos Tatas , G. Koutroumpezis , D. J. Soudris , Adonios Thanailakis An Integrated Framework for Architecture Level Exploration of Reconfigurable Platform. [Citation Graph (0, 0)][DBLP ] Conf ] Boris Ratchev , Mike Hutton , David Mendel Coping With Uncertainty in FPGA Architecture Design. [Citation Graph (0, 0)][DBLP ] Conf ] Naoki Iwanaga , Yuichiro Shibata , Masato Yoshimi , Yasunori Osana , Yow Iwaoka , Tomonori Fukushima , Hideharu Amano , Akira Funahashi , Noriko Hiroi , Hiroaki Kitano , Kiyoshi Oguri Efficient Scheduling of Rate Law Functions for ODE-Based Multimodel Biochemical Simulation on an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Pierre Deschamps , Gustavo Sutter Finite Field Division Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Faes , Mark Christiaens , Dries Buytaert , Dirk Stroobandt FPGA-Aware Garbage Collection in Java. [Citation Graph (0, 0)][DBLP ] Conf ] Allen Michalski , Kris Gaj , Duncan A. Buell High-Throughput Reconfigurable Computing: A Design Study of an IDEA Encryption Cryptosystem on the SRC-6e Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Nicolas Bruchon , Gaston Cambon , Lionel Torres , Gilles Sassatelli Magnetic remanent memory structures for dynamically reconfigurable fine grain FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen Hung Tsoi , Philip Heng Wai Leong Mullet - A Parallel Multiplier Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Zadnik , Tomas Pecenka , Jan Korenek NetFlow Probe Intended for High-Speed Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Zdenek Pohl , Premysl Sucha , Jiri Kadlec , Zdenek Hanzálek Performance Tuning of Iterative Algorithms in Signal Processing. [Citation Graph (0, 0)][DBLP ] Conf ] Pascal Benoit , Jürgen Becker , Michel Robert , Lionel Torres , Gilles Sassatelli , Gaston Cambon Run-Time Scheduling for Random Multi-Tasking in Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] K. Siozios , Dimitrios Soudris , Adonios Thanailakis A Low-Energy FPGA: Architecture Design and Software-Supported Design Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Frank Honoré A Power-Performance Scalable FPGA Using Configurable Voltage Domains and Design Mapping Tool. [Citation Graph (0, 0)][DBLP ] Conf ] Luis E. Cordova , Duncan A. Buell An Approach to Scalable Molecular Dynamics Simulation Using Supercomputing Adaptive Processing Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Kuen Hung Tsoi Computer Arithmetic Synthesis Technologies on Reconfigurable Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Te Ewe Dual FiXed-point : An Efficient Alternative to Floating-point Computation for DSP applications. [Citation Graph (0, 0)][DBLP ] Conf ] Florian Dittmann Efficient Execution on Reconfigurable Devices Using Concepts of Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Alastair M. Smith Exploration of Heterogeneous Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Fernando Pardo , P. López , Diego Cabello , M. Balsi FPGA Finite-Difference Time-Domain solver for thermal simulation. [Citation Graph (0, 0)][DBLP ] Conf ] F. Javier Toledo , J. Javier Martínez , F. Javier Garrigós , José Manuel Ferrández FPGA Implementation of an Augmented Reality Application for Visually Impaired People. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Campregher FPGA Interconnect Fault tolerance. [Citation Graph (0, 0)][DBLP ] Conf ] Kurian Oommen , David Harle Hardware Emulation of a Network on Chip Architecture based on a Clockwork Routed Manhattan Street Network. [Citation Graph (0, 0)][DBLP ] Conf ] János Lazányi Instruction Set Extension Using Microblaze Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Lesley Shannon , Paul Chow Leveraging Reconfigurability in the Design Process. [Citation Graph (0, 0)][DBLP ] Conf ] Martin J. Pearson MechanoProcessor: Modelling the Rodent Whisker Sensory System using FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshee P. Bharadwaj Next Generation Architectures and CAD for Power Aware Programmable Fabrics. [Citation Graph (0, 0)][DBLP ] Conf ] Renqiu Huang , Ranga Vemuri PAHLS: Towards Run-Time Synthesis for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] David Nguyen Reconfigurable Architectures for Real-Time Network Anomaly Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Hiren Joshi , S. S. Verma , G. K. Sharma Requested-QoS Driven Runtime Reconfiguration of Mobile Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Thomas Design of a Dynamic Reconfigurable Multi-Grained Hardware Architecture with Adaptive Runtime Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Virendra Singh , Michiko Inoue , Kewal K. Saluja , Hideo Fujiwara Testing Superscalar Processors in Functional Mode. [Citation Graph (0, 0)][DBLP ] Conf ] 