Conferences in DBLP
Wim Roelandts FPGAs and the Era of Field Programmability. [Citation Graph (0, 0)][DBLP ] Conf ] Nick Tredennick , Brion Shimamoto Reconfigurable Systems Emerge. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Dickinson System-Level Design Tools Can Provide Low Cost Solutions in FPGAs: TRUE or FALSE? [Citation Graph (0, 0)][DBLP ] Conf ] Anish Alex , Jonathan Rose , Ruth Isserlin-Weinberger , Christopher W. V. Hogue Hardware Accelerated Novel Protein Identification. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Dydel , Piotr Bala Large Scale Protein Sequence Alignment Using FPGA Reprogrammable Logic Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Graf , Peter M. Athanas A Key Management Architecture for Securing Off-Chip Data Transfers. [Citation Graph (0, 0)][DBLP ] Conf ] Celia López-Ongil , Raul Sánchez-Reillo , Judith Liu-Jimenez , Fernando Casado , Leslie Sánchez , Luis Entrena FPGA Implementation of Biometric Authentication System Based on Hand Geometry. [Citation Graph (0, 0)][DBLP ] Conf ] Tero Rissa , Peter Y. K. Cheung , Wayne Luk SoftSONIC: A Customisable Modular Platform for Video Applications. [Citation Graph (0, 0)][DBLP ] Conf ] A. Bigot , F. Charpentier , Helena Krupnova , I. Sans Deploying Hardware Platforms for SoC Validation: An Industrial Case Study. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Kerins , Emanuel M. Popovici , William P. Marnane Algorithms and Architectures for Use in FPGA Implementations of Identity Based Encryption Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] François-Xavier Standaert , Siddika Berna Örs , Jean-Jacques Quisquater , Bart Preneel Power Analysis Attacks Against FPGA Implementations of the DES. [Citation Graph (0, 0)][DBLP ] Conf ] Maya Gokhale , Janette Frigo , Christine Ahrens , Justin L. Tripp , Ronald Minnich Monte Carlo Radiative Heat Transfer Simulation on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Yoshimi , Yasunori Osana , Tomonori Fukushima , Hideharu Amano Stochastic Simulation for Biochemical Reactions on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Thomas , Jürgen Becker Dynamic Adaptive Runtime Routing Techniques in Multigrain Reconfigurable Hardware Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Frederick C. Furtek , Eugene Hogenauer , James Scheuermann Interconnecting Heterogeneous Nodes in an Adaptive Computing Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Hutton , Jay Schleicher , David M. Lewis , Bruce Pedersen , Richard Yuan , Sinan Kaptanoglu , Gregg Baeckler , Boris Ratchev , Ketan Padalia , Mark Bourgeault , Andy Lee , Henry Kim , Rahul Saini Improving FPGA Performance and Area Using an Adaptive Logic Module. [Citation Graph (0, 0)][DBLP ] Conf ] Aman Gayasen , K. Lee , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin , Tim Tuan A Dual-VDD Low Power FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Gang Chen , Jason Cong Simultaneous Timing Driven Clustering and Placement for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Helge Anderson , Sudip Nag , Kamal Chaudhary , Sandor Kalman , Chari Madabhushi , Paul Cheng Run-Time-Conscious Automatic Timing-Driven FPGA Layout Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Andrea Lodi , Roberto Giansante , Carlo Chiesa , Luca Ciccarelli , Fabio Campi , Mario Toma Compact Buffered Routing Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Hongbing Fan , Yu-Liang Wu , Chak-Chung Cheung , Jiping Liu On Optimal Irregular Switch Box Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Chun Te Ewe , Peter Y. K. Cheung , George A. Constantinides Dual Fixed-Point: An Efficient Alternative to Floating-Point Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Gustavo Sutter , Gery Bioul , Jean-Pierre Deschamps Comparative Study of SRT-Dividers in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Jérémie Detrey , Florent de Dinechin Second Order Function Approximation Using a Single Multiplication on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Guerric Meurice de Dormale , Philippe Bulens , Jean-Jacques Quisquater Efficient Modular Division Implementation: ECC over GF(p) Affine Coordinates Application. [Citation Graph (0, 0)][DBLP ] Conf ] Jesús Tabero , Julio Septién , Hortensia Mecha , Daniel Mozos A Low Fragmentation Heuristic for Task Placement in 2D RTR HW Management. [Citation Graph (0, 0)][DBLP ] Conf ] Sebastian Lange , Martin Middendorf The Partition into Hypercontexts Problem for Hyperreconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Minoru Watanabe , Fuminori Kobayashi A High-Density Optically Reconfigurable Gate Array Using Dynamic Method. [Citation Graph (0, 0)][DBLP ] Conf ] Didier Keymeulen , Ricardo Salem Zebulum , Adrian Stoica , Vu Duong , Michael I. Ferguson Evolvable Hardware for Signal Separation and Noise Cancellation Using Analog Reconfigurable Device. [Citation Graph (0, 0)][DBLP ] Conf ] Eduardo Picatoste-Olloqui , Francisco Cardells-Tormo , Jordi Sempere-Agulló , Atilà Herms-Berenguer Implementing High-Speed Double-Data Rate (DDR) SDRAM Controllers on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Fatih Kocan , Jason Meyer Logic Modules with Shared SRAM Tables for Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] David V. Schuehler , John W. Lockwood A Modular System for FPGA-Based TCP Flow Processing in High-Speed Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Zachary K. Baker , Viktor K. Prasanna Automatic Synthesis of Efficient Intrusion Detection Systems on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Nicola Campregher , Peter Y. K. Cheung , Milan Vasilko BIST Based Interconnect Fault Location for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] A. Parreira , João Paulo Teixeira , Marcelino B. Santos FPGAs BIST Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] C. J. Tavares , C. Bungardean , G. M. Matos , José T. de Sousa Solving SAT with a Context-Switching Virtual Clause Pipeline and an FPGA Embedded Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Peeter Ellervee , Jaan Raik , Valentin Tihhomirov , Kalle Tammemäe Evaluating Fault Emulation on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Dong-U Lee , Oskar Mencer , David J. Pearce , Wayne Luk Automating Optimized Table-with-Polynomial Function Evaluation for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Nalin Sidahao , George A. Constantinides , Peter Y. K. Cheung Multiple Restricted Multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Meyer-Bäse , Suhasini Rao , Javier Ramírez , Antonio García Area*Time Optimized Hogenauer Channelizer Design Using FPL Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Christos-Savvas Bouganis , Peter Y. K. Cheung , Jeffrey Ng , Anil A. Bharath A Steerable Complex Wavelet Construction and Its Implementation on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Gordon J. Brebner Programmable Logic Has More Computational Power than Fixed Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandra Poetter , Jesse Hunter , Cameron Patterson , Peter M. Athanas , Brent E. Nelson , Neil Steiner JHDLBits: The Merging of Two Worlds. [Citation Graph (0, 0)][DBLP ] Conf ] Changchun Shi , James Hwang , Scott McMillan , Ann Root , Vinay Singh A System Level Resource Estimation Tool for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Elena Moscu Panainte , Koen Bertels , Stamatis Vassiliadis The PowerPC Backend Molen Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Handa , Ranga Vemuri An Integrated Online Scheduling and Placement Methodology. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Ullmann , Michael Hübner , Björn Grimm , Jürgen Becker On-Demand FPGA Run-Time System for Dynamical Reconfiguration with Adaptive Priorities. [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Takeshi Inuo , Hirokazu Kami , Taro Fujii , Masayasu Suzuki Techniques for Virtual Hardware on a Dynamically Reconfigurable Processor - An Approach to Tough Cases. [Citation Graph (0, 0)][DBLP ] Conf ] Marcos R. Boschetti , Sergio Bampi , Ivan Saraiva Silva Throughput and Reconfiguration Time Trade-Offs: From Static to Dynamic Reconfiguration in Dedicated Image Filters. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Sugawara , Mary Inaba , Kei Hiraki Over 10Gbps String Matching Mechanism for Multi-stream Packet Scanning Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ma José Canet , Felip Vicedo , Vicenc Almenar-Terre , Javier Valls-Coquillat , Eduardo R. de Lima Hardware Design of a FPGA-Based Synchronizer for Hiperlan/2. [Citation Graph (0, 0)][DBLP ] Conf ] Yoshiki Yamaguchi , Tsutomu Maruyama , Akihiko Konagaya Three-Dimensional Dynamic Programming for Homology Search. [Citation Graph (0, 0)][DBLP ] Conf ] Shin'ichi Wakabayashi , Kenji Kikuchi An Instance-Specific Hardware Algorithm for Finding a Maximum Clique. [Citation Graph (0, 0)][DBLP ] Conf ] Ralf Ludewig , Oliver Soffke , Peter Zipf , Manfred Glesner , Kong Pang Pun , Kuen Hung Tsoi , Kin-Hong Lee , Philip Heng Wai Leong IP Generation for an FPGA-Based Audio DAC Sigma-Delta Converter. [Citation Graph (0, 0)][DBLP ] Conf ] Mark Holland , Scott Hauck Automatic Creation of Reconfigurable PALs/PLAs for SoC. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Denning , James Irvine , Malachy Devlin A Key Agile 17.4 Gbit/sec Camellia Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Viktor Fischer , Milos Drutarovský , Martin Simka , Nathalie Bochard High Performance True Random Number Generator in Altera Stratix FPLDs. [Citation Graph (0, 0)][DBLP ] Conf ] Norbert Pramstaller , Johannes Wolkerstorfer A Universal and Efficient AES Co-processor for Field Programmable Logic Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Zambreno , David Nguyen , Alok N. Choudhary Exploring Area/Delay Tradeoffs in an AES FPGA Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep S. Kumar , Christof Paar Reconfigurable Instruction Set Extension for Enabling ECC on an 8-Bit Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Miljan Vuletic , Laura Pozzi , Paolo Ienne Dynamic Prefetching in the Virtual Memory Window of Portable Reconfigurable Coprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Dalia Dagher , Iyad Ouaiss Storage Allocation for Diverse FPGA Memory Specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Javier Díaz , Eduardo Ros , Sonia Mota , Richard R. Carrillo , Rodrigo Agís Real Time Optical Flow Processing System. [Citation Graph (0, 0)][DBLP ] Conf ] Tim Todman , Wayne Luk Methods and Tools for High-Resolution Imaging. [Citation Graph (0, 0)][DBLP ] Conf ] Andrei Bartic , Dirk Desmet , Jean-Yves Mignolet , Théodore Marescaux , Diederik Verkest , Serge Vernalde , Rudy Lauwereins , J. Miller , Frédéric Robert Network-on-Chip for Reconfigurable Systems: From High-Level Design Down to Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Layer , Hans-Jörg Pfleiderer A Reconfigurable Recurrent Bitonic Sorting Network for Concurrently Accessible Data. [Citation Graph (0, 0)][DBLP ] Conf ] Sumit Mohanty , Viktor K. Prasanna A Framework for Energy Efficient Design of Multi-rate Applications Using Hybrid Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jawad Khan , Ranga Vemuri An Efficient Battery-Aware Task Scheduling Methodology for Portable RC Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Holger Lange , Andreas Koch HW/SW Co-design by Automatic Embedding of Complex IP Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Claudiu Zissulescu , Bart Kienhuis , Ed F. Deprettere Increasing Pipelined IP Core Utilization in Process Networks Using Exploration. [Citation Graph (0, 0)][DBLP ] Conf ] Rawat Siripokarpirom Distribution of Bitstream-Level IP Cores for Functional Evaluation Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Arthur Segard , François Verdier SOC and RTOS: Managing IPs and Tasks Communications. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. E. Wilton , Su-Shin Ang , Wayne Luk The Impact of Pipelining on Energy per Operation in Field-Programmable Gate Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Jingzhao Ou , Viktor K. Prasanna A Methodology for Energy Efficient FPGA Designs Using Malleable Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Rajarshi Mukherjee , Seda Ogrenci Memik Power-Driven Design Partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Michael G. Lorenz , Luis Mengibar , Mario García-Valderas , Luis Entrena Power Consumption Reduction Through Dynamic Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Mihail Petrov , Tudor Murgan , F. May , Martin Vorbach , Peter Zipf , Manfred Glesner The XPP Architecture and Its Co-simulation Within the Simulink Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Muhammad Atif Tahir , Ahmed Bouridane , Fatih Kurugollu An FPGA Based Coprocessor for the Classification of Tissue Patterns in Prostatic Cancer. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Köhler , Jens Braunes , Thomas Preußer , Martin Zabel , Rainer G. Spallek Increasing ILP of RISC Microprocessors Through Control-Flow Based Reconfiguration. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Hinkelbein , Andrei Khomich , Andreas Kugel , Reinhard Männer , Matthias Müller Using of FPGA Coprocessor for Improving the Execution Speed of the Pattern Recognition Algorithm for ATLAS - High Energy Physics Experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Brandon Blodget , Christophe Bobda , Michael Hübner , Adronis Niyonkuru Partial and Dynamically Reconfiguration of Xilinx Virtex-II FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Donlin , Axel Braun , Adam Rose SystemC for the Design and Modeling of Programmable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jim Torresen An Evolvable Hardware Tutorial. [Citation Graph (0, 0)][DBLP ] Conf ] Herbert Walder , Marco Platzner A Runtime Environment for Reconfigurable Hardware Operating Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Xin Jia , Jayanthi Rajagopalan , Ranga Vemuri A Dynamically Reconfigurable Asynchronous FPGA Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Björn Griese , Erik Vonnahme , Mario Porrmann , Ulrich Rückert Hardware Support for Dynamic Reconfiguration in Reconfigurable SoC Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Ahmadinia , Christophe Bobda , Sándor P. Fekete , Jürgen Teich , Jan van der Veen Optimal Routing-Conscious Dynamic Placement for Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Danilin , Sergei Sawitzki Optimizing the Performance of the Simulated Annealing Based Placement Algorithms for Island-Style FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Shawn Phillips , Akshay Sharma , Scott Hauck Automating the Layout of Reconfigurable Subsystems via Template Reduction. [Citation Graph (0, 0)][DBLP ] Conf ] Tom Van Court , Yongfeng Gu , Martin C. Herbordt FPGA Acceleration of Rigid Molecule Interactions. [Citation Graph (0, 0)][DBLP ] Conf ] Michalis D. Galanis , George Theodoridis , Spyros Tragoudas , Dimitrios Soudris , Constantinos E. Goutis Mapping DSP Applications to a High-Performance Reconfigurable Coarse-Grain Data-Path. [Citation Graph (0, 0)][DBLP ] Conf ] Cristinel Ababei , Pongstorn Maidee , Kia Bazargan Exploring Potential Benefits of 3D FPGA Integration. [Citation Graph (0, 0)][DBLP ] Conf ] Yang Qu , Kari Tiensyrjä , Kostas Masselos System-Level Modeling of Dynamically Reconfigurable Co-processors. [Citation Graph (0, 0)][DBLP ] Conf ] João Canas Ferreira , José Silva Matos A Development Support System for Applications That Use Dynamically Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Bansal , Sumit Gupta , Nikil D. Dutt , Alexandru Nicolau , Rajesh K. Gupta Interconnect-Aware Mapping of Applications to Coarse-Grain Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Renqiu Huang , Manish Handa , Ranga Vemuri Analysis of a Hybrid Interconnect Architecture for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Hossam A. ElGindy , George Ferizis Mapping Basic Recursive Structures to Runtime Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Takehiro Ito , Yuichiro Shibata , Kiyoshi Oguri Implementation of the Extended Euclidean Algorithm for the Tate Pairing on FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Schoeberl Java Technology in an FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Valery Sklyarov , Iouliia Skliarova , Bruno S. Pimentel , Joel Arrais Hardware/Software Implementation of FPGA-Targeted Matrix-Oriented SAT Solvers. [Citation Graph (0, 0)][DBLP ] Conf ] Chrilly Donninger , Ulf Lorenz The Chess Monster Hydra. [Citation Graph (0, 0)][DBLP ] Conf ] Ireneusz Janiszewski , Hermann Meuth , Bernhard Hoppe FPGA-Efficient Hybrid LUT/CORDIC Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Oliver A. Pfänder , Roland Hacker , Hans-Jörg Pfleiderer A Multiplexer-Based Concept for Reconfigurable Multiplier Arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Cesar Torres-Huitzil , René Cumplido-Parra , Santos López-Estrada Design and Implementation of a CFAR Processor for Target Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph Palmer , Brent E. Nelson A Parallel FFT Architecture for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Marcos Martínez Peiró , Francisco Ballester , Guillermo Payá Vayá , Ricardo José Colom-Palero , Rafael Gadea Gironés , J. Belenguer FPGA Custom DSP for ECG Signal Analysis and Compression. [Citation Graph (0, 0)][DBLP ] Conf ] Quoc Thai Ho , Daniel Massicotte FPGA Implementation of Adaptive Multiuser Detector for DS-CDMA Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Unai Bidarte , Armando Astarloa , José Luis Martín , Jon Andreu Simulation Platform for Architectural Verification and Performance Analysis in Core-Based SoC Design. [Citation Graph (0, 0)][DBLP ] Conf ] Erik Schüler , Luigi Carro A Low Power FPAA for Wide Band Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Edson L. Horta , John W. Lockwood Automated Method to Generate Bitstream Intellectual Property Cores for Virtex FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tsutomu Maruyama Real-Time Computation of the Generalized Hough Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Joaquín Olivares , Javier Hormigo , Julio Villalba , Ignacio Benavides Minimum Sum of Absolute Differences Implementation in a Single FPGA Device. [Citation Graph (0, 0)][DBLP ] Conf ] Faycal Bensaali , Abbes Amira Design and Efficient FPGA Implementation of an RGB to YCrCb Color Space Converter Using Distributed Arithmetic. [Citation Graph (0, 0)][DBLP ] Conf ] Jesús Lázaro , Armando Astarloa , Jagoba Arias , Unai Bidarte , Carlos Cuadrado High Throughput Serpent Encryption Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Sashisu Bajracharya , Chang Shu , Kris Gaj , Tarek A. El-Ghazawi Implementation of Elliptic Curve Cryptosystems over GF(2n ) in Optimal Normal Basis on a Reconfigurable Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Hagen Gädke , Andreas Koch Wavelet-Based Image Compression on the Reconfigurable Computer ACE-V. [Citation Graph (0, 0)][DBLP ] Conf ] María Dolores Valdés , Miguel A. Domínguez , María José Moure , Camilo Quintáns A Reconfigurable Communication Processor Compatible with Different Industrial Fieldbuses. [Citation Graph (0, 0)][DBLP ] Conf ] Philip James-Roxby , Gordon J. Brebner Multithreading in a Hyper-programmable Platform for Networked Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ricardo Ferreira , João M. P. Cardoso , Horácio C. Neto An Environment for Exploring Data-Driven Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Mannino , Hassan Rabah , Camel Tanougast , Yves Berviller , Michael Janiaut , Serge Weber FPGA Implementation of a Novel All Digital PLL Architecture for PCR Related Measurements in DVB-T. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Bobda , Mateusz Majer , Dirk Koch , Ali Ahmadinia , Jürgen Teich A Dynamic NoC Approach for Communication in Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Hübner , Michael Ullmann , Lars Braun , A. Klausmann , Jürgen Becker Scalable Application-Dependent Network on Chip Adaptivity for Dynamical Reconfigurable Real-Time Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Leandro Möller , Ney Laert Vilar Calazans , Fernando Gehm Moraes , Eduardo Wenzel Brião , Ewerson Carvalho , Daniel Camozzato FiPRe: An Implementation Model to Enable Self-Reconfigurable Applications. [Citation Graph (0, 0)][DBLP ] Conf ] N. Pete Sedcole , Peter Y. K. Cheung , George A. Constantinides , Wayne Luk A Structured Methodology for System-on-an-FPGA Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kris Tiri , Ingrid Verbauwhede Secure Logic Synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] M. G. Valderas , Eduardo de la Torre , F. Ariza , Teresa Riesgo Hardware and Software Debugging of FPGA Based Microprocessor Systems Through Debug Logic Insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Jonathan Noel Tombs , Miguel Angel Aguirre Echánove , Fernando Muñoz Chavero , Vicente Baena Lecuyer , Antonio Jesús Torralba Silgado , A. Fernandez-León , Francisco Tortosa The Implementation of a FPGA Hardware Debugger System with Minimal System Overhead. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Optimization of Testability of Sequential Circuits Implemented in FPGAs with Embedded Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Chris Clarke , Lin Qiang , Herbert Peremans , Álvaro Hernández FPGA Implementation of a Neuromimetic Cochlea for a Bionic Bat Head. [Citation Graph (0, 0)][DBLP ] Conf ] Terrence S. T. Mak , K. P. Lam FPGA-Based Computation for Maximum Likelihood Phylogenetic Tree Evaluation. [Citation Graph (0, 0)][DBLP ] Conf ] Albert A. Conti , Tom Van Court , Martin C. Herbordt Processing Repetitive Sequence Structures with Mismatches at Streaming Rate. [Citation Graph (0, 0)][DBLP ] Conf ] Pedro Ferreira , Pedro Ribeiro , Ana Antunes , Fernando Morgado Dias Artificial Neural Networks Processor - A Hardware Implementation Using a FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Enrique Cantó , Nicolau Canyellas , Mariano Fons , Francisco Fons , Mariano López FPGA Implementation of the Ridge Line Following Fingerprint Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Thilo Pionteck , Thomas Stiefmeier , Thorsten Staake , Manfred Glesner A Dynamically Reconfigurable Function-Unit for Error Detection and Correction in Mobile Terminals. [Citation Graph (0, 0)][DBLP ] Conf ] David Nguyen , Joseph Zambreno , Gokhan Memik Flow Monitoring in High-Speed Networks with 2D Hash Tables. [Citation Graph (0, 0)][DBLP ] Conf ] Kimmo U. Järvinen , Matti Tommiska , Jorma Skyttä A VHDL Generator for Elliptic Curve Cryptography. [Citation Graph (0, 0)][DBLP ] Conf ] Alessandro Bogliolo , Valerio Freschi , Filippo Miglioli , Matteo Canella FPGA-Based Parallel Comparison of Run-Length-Encoded Strings. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Manuel García Chamizo , Andrés Fuster Guilló , Jorge Azorín López Real Environments Image Labelling Based on Reconfigurable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Borgosz Object Oriented Programming Paradigms for the VHDL. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan Gonzalez , Javier Sanchez-Pastor , Jorge L. Hernandez-Ardieta , Francisco J. Gomez-Arribas , Javier Martínez Using Reconfigurable Hardware Through Web Services in Distributed Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Nastaran Baradaran , Joonseok Park , Pedro C. Diniz Data Reuse in Configurable Architectures with RAM Blocks: Extended Abstract. [Citation Graph (0, 0)][DBLP ] Conf ] K. Siozios , G. Koutroumpezis , Konstantinos Tatas , Dimitrios Soudris , Adonios Thanailakis A Novel FPGA Configuration Bitstream Generation Algorithm and Tool Development. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Niang , Thierry Grandpierre , Mohamed Akil , Yves Sorel AAA and SynDEx-Ic: A Methodology and a Software Framework for the Implementation of Real-Time Applications onto Reconfigurable Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Armando Astarloa , Jesús Lázaro , Unai Bidarte , José Luis Martín , Aitzol Zuloaga A Self-Reconfiguration Framework for Multiprocessor CSoPCs. [Citation Graph (0, 0)][DBLP ] Conf ] Adam Donlin , Patrick Lysaght , Brandon Blodget , Gerd Troeger A Virtual File System for Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Tapio Ristimäki , Jari Nurmi Virtualizing the Dimensions of a Coarse-Grained Reconfigurable Array. [Citation Graph (0, 0)][DBLP ] Conf ] Tomás Marek , Martin Novotný , Ludek Crha Design and Implementation of the Memory Scheduler for the PC-Based Router. [Citation Graph (0, 0)][DBLP ] Conf ] Eric E. Fabris , Luigi Carro , Sergio Bampi Analog Signal Processing Reconfiguration for Systems-on-Chip Using a Fixed Analog Cell Approach. [Citation Graph (0, 0)][DBLP ] Conf ] Luis Parrilla , Encarnación Castillo , Antonio García , Antonio Lloris-Ruíz Intellectual Property Protection for RNS Circuits on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] René de Jesús Romero-Troncoso , Gilberto Herrera Ruiz FPGA Implementation of a Tool Breakage Detection Algorithm in CNC Milling Machines. [Citation Graph (0, 0)][DBLP ] Conf ] Milos Drutarovský , Viktor Fischer Implementation of a 3-D Switching Median Filtering Scheme with an Adaptive LUM-Based Noise Detector. [Citation Graph (0, 0)][DBLP ] Conf ] Jan Schier , Antonin Hermanek Using Logarithmic Arithmetic to Implement the Recursive Least Squares (QR) Algorithm in FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Viorela Ila , Rafael García , François Charot , Joan Batlle FPGA Implementation of a Vision-Based Motion Estimation Algorithm for an Underwater Robot. [Citation Graph (0, 0)][DBLP ] Conf ] Hiroaki Niitsuma , Tsutomu Maruyama Real-Time Detection of Moving Objects. [Citation Graph (0, 0)][DBLP ] Conf ] Sonia Mota , Eduardo Ros , Javier Díaz , Eva M. Ortigosa , Rodrigo Agís , Richard R. Carrillo Real-Time Visual Motion Detection of Overtaking Cars for Driving Assistance Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Pierre Chalimbaud , François Berry Versatile Imaging Architecture Based on a System on Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Constantinos Skarpathiotis , Keith R. Dimond A Hardware Implementation of a Content Based Image Retrieval Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Ahmadinia Optimization Algorithms for Dynamic Reconfigurable Embedded Systems p. [Citation Graph (0, 0)][DBLP ] Conf ] Aman Gayasen Low Power Reconfigurable Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Brian F. Veale , John K. Antonio , Monte P. Tull Code Re-ordering for a Class of Reconfigurable Microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Haubelt Design Space Exploration for Distributed Hardware Reconfigurable Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Cristinel Ababei TPR: Three-D Place and Route for FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] David B. Thomas , Wayne Luk Implementing Graphics Shaders Using FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Koch Preemptive Hardware Task Management. [Citation Graph (0, 0)][DBLP ] Conf ] Graham Schelle , Dirk Grunwald Automated Speculation and Parallelism in High Performance Network Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Heidi E. 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Cheung A System on Chip Design Framework for Prime Number Validation Using Reconfigurable Hardware. [Citation Graph (0, 0)][DBLP ] Conf ] Terrence S. T. Mak , K. P. Lam On Computing Maximum Likelihood Phylogeny Using FPGA p. [Citation Graph (0, 0)][DBLP ] Conf ] Usama Malik Minimising Reconfiguration Overheads in Embedded Applications (Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Vinu Vijay Kumar Application Specific Small-Scale Reconfigurability. [Citation Graph (0, 0)][DBLP ] Conf ] Zachary K. Baker Efficient FPGA-Based Security Kernels. [Citation Graph (0, 0)][DBLP ] Conf ] 