Conferences in DBLP
Yun-Nan Chang , Ching-Yi Wang , Keshab K. Parhi Loop-List Scheduling for Heterogeneous Functional Units. [Citation Graph (0, 0)][DBLP ] Conf ] Duen-Jeng Wang , Yu Hen Hu Synthesis of Real-Time Recursive DSP Algorithms Using Multiple Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Jian-Feng Shi , Liang-Fang Chao Resource-Constrained Algebraic Transformation for Loop Pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Gary William Grewal A Global Mode Instruction Minimization Technique for Embedded DSPs. [Citation Graph (0, 0)][DBLP ] Conf ] Philippe Royannez , Amara Amara A 1.0ns 64-bits GaAs Adder using Quad tree algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Nalini K. Ratha , Anil K. Jain , Diane T. Rover FPGA-based high performance page layout segmentation. [Citation Graph (0, 0)][DBLP ] Conf ] Pong P. Chu A Reprogrammable FPGA-Based ATM Traffic Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Kevin A. Kwiat , Warren Debany , Salim Hariri Software Fault Tolerance Using Dynamically Reconfigurable FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Moazzem Hossain , Bala Thumma , Sunil Ashtaputre A New Faster Algorithm for Iterative Placement Improvement. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Stroobandt , Herwig Van Marck , Jan Van Campenhout An Accurate Interconnection Length Estimation for Computer Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Dinesh P. Mehta , Naveed A. Sherwani A Minimum-Area Floorplanning Algorithm for MBC Designs. [Citation Graph (0, 0)][DBLP ] Conf ] Jianjian Song , Heng Kek Choo , Wenjun Zhuang A New Model for General Connectivity and its Application to Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Nelson L. Passos , Edwin Hsing-Mean Sha A Parameterized Index-Generator for the Multi-Dimensional Interleaving Optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Paul Shipley , Sherif Sayed , Magdy A. Bayoumi A High Speed VLSI Architecture for Scaleable ATM Switches. [Citation Graph (0, 0)][DBLP ] Conf ] Jörg Wilberg , A. Kuth , Raul Camposano , Wolfgang Rosenstiel , Heinrich Theodor Vierhaus A Design Exploration Environment. [Citation Graph (0, 0)][DBLP ] Conf ] Mariana-Eugenia Petre , Guido Masera A Parametrical Architecture for Reed-Solomon Decoders. [Citation Graph (0, 0)][DBLP ] Conf ] Joseph L. Ganley , James P. Cohoon A Provably Good Moat Routing Algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Anthony D. Johnson On Locally Optimal Breaking of Complex Cyclic Vertical Constraints in VLSI Channel Routing. [Citation Graph (0, 0)][DBLP ] Conf ] James Loy , Atul Garg , Mukkai S. Krishnamoorthy , John F. McDonald Chip Pad Migration is a Key Component to High Performance MCM Design. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan An Optimal ILP Formulation for Minimixing the Number of Feedthrough Cells in Standard Cell Placement. [Citation Graph (0, 0)][DBLP ] Conf ] Sofiène Tahar , Zijian Zhou , Xiaoyu Song , Eduard Cerny , Michel Langevin Formal Verification of an ATM Switch Fabric using Multiway Decision Graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Valeria Bertacco , Maurizio Damiani Boolean Function Representation Using Parallel-Access Diagrams. [Citation Graph (0, 0)][DBLP ] Conf ] Chien-Chung Tsai , Malgorzata Marek-Sadowska Logic Synthesis for Testability. [Citation Graph (0, 0)][DBLP ] Conf ] Seokjin Kim , Ramalingam Sridhar Self-Timed Mesochronous Interconnection for High-Speed VLSI Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Laura Heinrich-Litan , Paul Molitor , Dirk Möller Least Upper Bounds on the Sizes of Symmetric Variable Order based OBDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Dongsheng Wang , Ernest S. Kuh Performance-Driven Interconnect Global Routing. [Citation Graph (0, 0)][DBLP ] Conf ] Manjit Borah , Robert Michael Owens , Mary Jane Irwin Recent Developments in Performance Driven Steiner Routing: An Overview. [Citation Graph (0, 0)][DBLP ] Conf ] Masato Edahiro , Richard J. Lipton Clock Buffer Placement Algorithm for Wire-Delay-Dominated Timing Model. [Citation Graph (0, 0)][DBLP ] Conf ] John Lillis , Chung-Kuan Cheng , Ting-Ting Y. Lin Simultaneous Routing and Buffer Insertion for High Performance Interconnect. [Citation Graph (0, 0)][DBLP ] Conf ] Guangqiu Chen , Hidetoshi Onodera , Keikichi Tamaru Timing and Power Optimization by Gate Sizing Considering False Paths. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Macii , Massimo Poncino Exact Computation of the Entropy of a Logic Circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Christophe Tretz , Charles A. Zukowski CMOS Transistor Sizing for Minimization of Energy-Delay Product. [Citation Graph (0, 0)][DBLP ] Conf ] Emad N. Farag , Mohamed I. Elmasry Low-Power Implementation of Discrete Cosine Transform. [Citation Graph (0, 0)][DBLP ] Conf ] Huzefa Mehta , Robert Michael Owens , Mary Jane Irwin Some Issues in Gray Code Addressing. [Citation Graph (0, 0)][DBLP ] Conf ] Prakash Arunachalam , Jacob A. Abraham , Manuel A. d'Abreu A Hierarchal Approach for Power Reduction in VLSI Chips. [Citation Graph (0, 0)][DBLP ] Conf ] Winfried Nöth , Uwe Hinsberger , Reiner Kolla TROY: A Tree-Based Approach to Logic Synthesis and Technology Mapping. [Citation Graph (0, 0)][DBLP ] Conf ] Bradley S. Carlson , C. Y. Roger Chen , Dikran S. Meliksetian Transistor Chaining in CMOS Leaf Cells of Planar Topology. [Citation Graph (0, 0)][DBLP ] Conf ] Mario A. Lopez , Dinesh P. Mehta Partitioning Algorithms for Corner Stitching. [Citation Graph (0, 0)][DBLP ] Conf ] Fabrizio Ferrandi , Franco Fummi , Enrico Macii , Massimo Poncino , Donatella Sciuto Test Generation for Networks of Interacting FSMs Using Symbolic Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Sankaran M. Menon , Anura P. Jayasumana , Yashwant K. Malaiya Input Pattern Classification for Transistor Level Testing of Bridging Faults in BiCMOS Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Nidhi Agrawal , Parul Agarwal , C. P. Ravikumar Efficient Delay Test Generation for Modular Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Hormoz Djahanshahi , Majid Ahmadi , Graham A. Jullien , William C. Miller Design and VLSI Implementation of a Unified Synapse-Neuron Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Chantana Chantrapornchai , Sissades Tongsima , Edwin Hsing-Mean Sha Rapid Prototyping for Fuzzy Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Hangu Yeo , Yu Hen Hu A Modular Architecture for Real Time HDTV Motion Estimation with Large Search Range. [Citation Graph (0, 0)][DBLP ] Conf ] José G. Delgado-Frias , Jabulani Nyathi , Chester L. Miller , Douglas H. Summerville A VLSI Interconnection Network Router Using a D-CAM with Hidden Refresh. [Citation Graph (0, 0)][DBLP ] Conf ] L. Desormeaux , V. Szwarc , J. Lodge A High-Speed, Real-to-Quadrature Converter with Filtering and Decimation. [Citation Graph (0, 0)][DBLP ] Conf ] Maher E. Rizkalla , Richard L. Aldridge , Nadeem A. Khan , Harry C. Gundrum A CMOS VLSI Implementation of an NxN Multiplexing Circuitry for ATM Applications. [Citation Graph (0, 0)][DBLP ] Conf ] Jai-Sop Hyun , Kwang Sub Yoon A 3V-50MHz Analog CMOS Current-Mode High Frequency Filter with a Negative Resistance Load. [Citation Graph (0, 0)][DBLP ] Conf ] Nozar Tabrizi , Michael J. Liebelt , Kamran Eshraghian Delay Hazards in Complex Gate Based Speed Independent VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ayman I. Kayssi Macromodeling C- and RC-loaded CMOS inverters for timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Shi-Yu Huang , Kwang-Ting Cheng , Kuang-Chien Chen On Verifying the Correctness of Retimed Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy , Janak H. Patel On Double Transition Faults as a Delay Fault Model. [Citation Graph (0, 0)][DBLP ] Conf ] Kent L. Einspahr , Sharad C. Seth , Vishwani D. Agrawal Improving Circuit Testability by Clock Control. [Citation Graph (0, 0)][DBLP ] Conf ] Zaifu Zhang , Robert D. McLeod An Efficient Multiple Scan Chain Testing Scheme. [Citation Graph (0, 0)][DBLP ] Conf ] 