Conferences in DBLP
Xinmiao Zhang , Keshab K. Parhi High-speed architectures for parallel long BCH encoders. [Citation Graph (0, 0)][DBLP ] Conf ] Adhir Upadhyay , Syed Rafay Hasan , Mohamed Nekili Optimal partitioning of globally asychronous locally synchronous processor arrays. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Davoodi , Vishal Khandelwal , Ankur Srivastava High level techniques for power-grid noise immunity. [Citation Graph (0, 0)][DBLP ] Conf ] Soroush Abbaspour , Amir H. Ajami , Massoud Pedram , Emre Tuncer TFA: a threshold-based filtering algorithm for propagation delay and slew calculation of high-speed VLSI interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Qinwei Xu , Pinaki Mazumder Modeling of transmission lines with EM wave coupling by the finite difference quadrature method. [Citation Graph (0, 0)][DBLP ] Conf ] Liang Zhang , Wentai Liu , Rizwan Bashirullah , John Wilson , Paul D. Franzon Simplified delay design guidelines for on-chip global interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Hassan Hassan , Mohab Anis , Mohamed I. Elmasry Design and optimization of MOS current mode logic for parameter variations. [Citation Graph (0, 0)][DBLP ] Conf ] Frank K. Gürkaynak , Andreas Burg , Norbert Felber , Wolfgang Fichtner , D. Gasser , F. Hug , Hubert Kaeslin A 2 Gb/s balanced AES crypto-chip implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Praveen Vellanki , Nilanjan Banerjee , Karam S. Chatha Quality-of-service and error control techniques for network-on-chip architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Yan , Dilip V. Sarwate Universal Reed-Solomon decoders based on the Berlekamp-Massey algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Tay-Jyi Lin , Hung-Yueh Lin , Chie-Min Chao , Chih-Wei Liu , Chein-Wei Jen A compact DSP core with static floating-point unit & its microcode generation. [Citation Graph (0, 0)][DBLP ] Conf ] Sankar Barua , Joan Carletta , Kishore A. Kotteri , Amy E. Bell An efficient architecture for lifting-based two-dimensional discrete wavelet transforms. [Citation Graph (0, 0)][DBLP ] Conf ] Alexey Lvov , Fook-Luen Heng A graph based simplex method for the integer minimum perturbation problem with sum and difference constraints. [Citation Graph (0, 0)][DBLP ] Conf ] Dave Nellans , Vamshi Krishna Kadaru , Erik Brunvand ARCS: an architectural level communication driven simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Stergios Stergiou , K. Daskalakis , George K. Papakonstantinou A fast and efficient heuristic ESOP minimization algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Gwenolé Corre , Eric Senn , Nathalie Julien , Eric Martin A memory aware behavioral synthesis tool for real-time VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shalini Ghosh , Eric MacDonald , Sugato Basu , Nur A. Touba Low-power weighted pseudo-random BIST using special scan cells. [Citation Graph (0, 0)][DBLP ] Conf ] Miroslav N. Velev Efficient formal verification of pipelined processors with instruction queues. [Citation Graph (0, 0)][DBLP ] Conf ] Hamidreza Hashempour , Fabrizio Lombardi Evaluation of heuristic techniques for test vector ordering. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Graziano Pravadelli Logic-level analysis of high-level faults. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Pillai , Harley Heinrich , K. V. S. Rao , Rene Martinez A stacked antenna broad-band RFID front-end for UHF and microwave bands. [Citation Graph (0, 0)][DBLP ] Conf ] Debayan Bhaduri , Sandeep K. Shukla NANOPRISM: a tool for evaluating granularity vs. reliability trade-offs in nano architectures. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Papa , Saurabh N. Adya , Igor L. Markov Constructive benchmarking for placement. [Citation Graph (0, 0)][DBLP ] Conf ] Ali Bastani , Charles A. Zukowski Design of superbuffers in sub-100nm CMOS technologies with significant gate leakage. [Citation Graph (0, 0)][DBLP ] Conf ] Jason W. Horihan , Yung-Hsiang Lu Improving FSM evolution with progressive fitness functions. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Shi , Yiorgos Makris Fault simulation and random test generation for speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jia Wang , Hai Zhou Minimal period retiming under process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Ottavi , Xiaopeng Wang , Fred J. Meyer , Fabrizio Lombardi Simulation of reconfigurable memory core yield. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-Ru Guo , Chao You , Paul F. Curran , Michael Chu , Kuan Zhou , Jiedong Diao , A. George , Russell P. Kraft , John F. McDonald The 10GHz 4: 1 MUX and 1: 4 DEMUX implemented via the gigahertz SiGe FPGA. [Citation Graph (0, 0)][DBLP ] Conf ] Ramyanshu Datta , Antony Sebastine , Ashwin Raghunathan , Jacob A. Abraham On-chip delay measurement for silicon debug. [Citation Graph (0, 0)][DBLP ] Conf ] Yarallah Koolivand , Ali Zahabi , Nasser Masoumi Modeling of polysilicide gate resistance effect on inverter delay and power consumption using distributed RC method and branching technique. [Citation Graph (0, 0)][DBLP ] Conf ] Zhengyu Wang , M. C. Frank Chang , Jessica Chiatai Chou A simple DDS architecture with highly efficient sine function lookup table. [Citation Graph (0, 0)][DBLP ] Conf ] A. Amirabadi , Javid Jaffari , Ali Afzali-Kusha , Mehrdad Nourani , Ali Khaki-Firooz Leakage current reduction by new technique in standby mode. [Citation Graph (0, 0)][DBLP ] Conf ] Tianyi Jiang , Xiaoyong Tang , Prithviraj Banerjee Macro-models for high level area and power estimation on FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Keoncheol Shin , Taewhan Kim Leakage power minimization for the synthesis of parallel multiplier circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ozcan Ozturk , Mahmut T. Kandemir , Mary Jane Irwin , Ibrahim Kolcu Tuning data replication for improving behavior of MPSoC applications. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , Abdelhalim Alsharqawi Self-resetting stage logic pipelines. [Citation Graph (0, 0)][DBLP ] Conf ] Shaolei Quan , Chin-Long Wey A noise optimization technique for codesign of CMOS radio-frequency low noise amplifiers and low-quality spiral inductors. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Moghaddam Tabrizi , Amir Amirabadi A CMOS elliptic low-pass switched capacitor ladder filter for video communication using bilinear implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Sudarshan Banerjee , Nikil D. Dutt FIFO power optimization for on-chip networks. [Citation Graph (0, 0)][DBLP ] Conf ] Cristian Grecu , Partha Pratim Pande , André Ivanov , Res Saleh Structured interconnect architecture: a solution for the non-scalability of bus-based SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Takashi Nojima , Yasuhiro Takashima , Shigetoshi Nakatake , Yoji Kajitani A device-level placement with multi-directional convex clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Paluszewski , Pawel Winter , Martin Zachariasen A new paradigm for general architecture routing. [Citation Graph (0, 0)][DBLP ] Conf ] Hasan Arslan , Shantanu Dutt An effective hop-based detailed router for FPGAs for optimizing track usage and circuit performance. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew B. Kahng , Igor L. Markov , Sherief Reda On legalization of row-based placements. [Citation Graph (0, 0)][DBLP ] Conf ] Yukiko Kubo , Hiroshi Miyashita , Yoji Kajitani , Kazuyuki Tateishi Equidistance routing in high-speed VLSI layout design. [Citation Graph (0, 0)][DBLP ] Conf ] Vishak Venkatraman , Atul Maheshwari , Wayne Burleson Mitigating static power in current-sensed interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Phillip Chin , Charles A. Zukowski , George Gristede , Stephen V. Kosonocky Characterization of logic circuit techniques for high leakage CMOS technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Bocca , Sabino Salerno , Enrico Macii , Massimo Poncino Energy-efficient bus encoding for LCD displays. [Citation Graph (0, 0)][DBLP ] Conf ] Yuantao Peng , Xun Liu Power macromodeling of global interconnects considering practical repeater insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Hiren D. Patel , Sandeep K. Shukla Towards a heterogeneous simulation kernel for system level models: a SystemC kernel for synchronous data flow models. [Citation Graph (0, 0)][DBLP ] Conf ] Shalini Ghosh , F. Joel Ferguson Estimating detection probability of interconnect opens using stuck-at tests. [Citation Graph (0, 0)][DBLP ] Conf ] Roghoyeh Salmeh , Brent Maundy VLSI implementation of an automatic Q tuning system. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar Mukherjee , Lei Wang , Andrea Pacelli A practical approach to modeling skin effect in on-chip interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Raoul F. Badaoui , Hemanth Sampath , Anuradha Agarwal , Ranga Vemuri A high level language for pre-layout extraction in parasite-aware analog circuit synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Guido Bertoni , Marco Macchetti , Luca Negri , Pasqualina Fragneto Power-efficient ASIC synthesis of cryptographic sboxes. [Citation Graph (0, 0)][DBLP ] Conf ] Hayward H. Chan , Igor L. Markov Practical slicing and non-slicing block-packing without simulated annealing. [Citation Graph (0, 0)][DBLP ] Conf ] Tun Li , Yang Guo , Sikun Li Assertion-based automated functional vectors generation using constraint logic programming. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Seok (Andy) Seo , Abhijit Chatterjee , Sang-Yeon Cho , Nan M. Jokerst Design and optimization of board-level optical clock distribution network for high-performance optoelectronic system-on-a-packages. [Citation Graph (0, 0)][DBLP ] Conf ] Wei Xu , Narayanan Vijaykrishnan , Yuan Xie , Mary Jane Irwin Design of a nanosensor array architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Edward K. S. Au , Wing-Hung Ki , Wai Ho Mow , Silas T. Hung , Catherine Y. Wong A binary--search switched--current sensing scheme for 4-state MRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Adam O. Lee , Robert J. Weber Design of a 5-Gb/s PRBS generator in 0.18µm CMOS process. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel Salim Maza , Mónico Linares Aranda Analysis and verification of interconnected rings as clock distribution networks. [Citation Graph (0, 0)][DBLP ] Conf ] Hongjoong Shin , Hak-soo Yu , Jacob A. Abraham LFSR-based BIST for analog circuits using slope detection. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey , Mohammad Athar Khalil , Jim Liu , Gregory Wierzba Hierarchical extreme-voltage stress test of analog CMOS ICs for gate-oxide reliability enhancement. [Citation Graph (0, 0)][DBLP ] Conf ] Ji Hwan (Paul) Chun , Hak-soo Yu , Jacob A. Abraham An efficient linearity test for on-chip high speed ADC and DAC using loop-back. [Citation Graph (0, 0)][DBLP ] Conf ] Ramprasad Ravichandran , Nihal Ladiwala , Jean Nguyen , Michael T. Niemier , Sung Kyu Lim Automatic cell placement for quantum-dot cellular automata. [Citation Graph (0, 0)][DBLP ] Conf ] Shamik Das , Anantha Chandrakasan , Rafael Reif Timing, energy, and thermal performance of three-dimensional integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Fengming Zhang , Rui Tang , Yong-Bin Kim SET-based nano-circuit simulation and design method using HSPICE. [Citation Graph (0, 0)][DBLP ] Conf ] Katsunori Tanaka , Shigeru Yamashita , Yahiko Kambayashi SPFD-based effective one-to-many rewiring (OMR) for delay reduction of LUT-based FPGA circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ambar A. Gadkari , S. Ramesh , Rubin A. Parekhji CESC: a visual formalism for specification and verification of SoCs. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth E. Batcher , Robert A. Walker Cluster miss prediction for instruction caches in embedded networking applications. [Citation Graph (0, 0)][DBLP ] Conf ] Fadi Busaba , Timothy J. Slegel , Steven R. Carlough , Christopher A. Krygowski , John G. Rell The design of the fixed point unit for the z990 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Zhen Guo How to reduce aliasing in linear analog testing. [Citation Graph (0, 0)][DBLP ] Conf ] Long Bu , John A. Chandy A keyword match processor architecture using content addressable memory. [Citation Graph (0, 0)][DBLP ] Conf ] Anh-Tuan Phan , Chang-Wan Kim , Min-Suk Kang , Sang-Gug Lee , Chun-Deok Su , Hoon-Tae Kim A high performance CMOS direct down conversion mixer for UWB system. [Citation Graph (0, 0)][DBLP ] Conf ] M. Reza Samadi , Aydin I. Karsilayan Multi-peak bandwidth enhancement technique for multistage amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas Eschbach , Wolfgang Günther , Bernd Becker Orthogonal hypergraph routing for improved visibility. [Citation Graph (0, 0)][DBLP ] Conf ] M. M. Vaseekar Kumar , Saravanan Padmanaban , Spyros Tragoudas Low power ATPG for path delay faults. [Citation Graph (0, 0)][DBLP ] Conf ] Rohini Krishnan , José Pineda de Gyvez , Martijn T. Bennebroek Low energy FPGA interconnect design. [Citation Graph (0, 0)][DBLP ] Conf ] David Zaretsky , Gaurav Mittal , Xiaoyong Tang , Prithviraj Banerjee Evaluation of scheduling and allocation algorithms while mapping assembly code onto FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kundan Nepal , Hui-Yuan Song , R. Iris Bahar , Joel Grodstein RESTA: a robust and extendable symbolic timing analysis tool. [Citation Graph (0, 0)][DBLP ] Conf ] Mirko Loghi , Massimo Poncino , Luca Benini Cycle-accurate power analysis for multiprocessor systems-on-a-chip. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Fazel , Lun Li , Mitchell A. Thornton , Robert B. Reese , Cherrice Traver Performance enhancement in phased logic circuits using automatic slack-matching buffer insertion. [Citation Graph (0, 0)][DBLP ] Conf ] C. Laoudias , Dimitris Nikolos A new test pattern generator for high defect coverage in a BIST environment. [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Dadda , Marco Macchetti , Jeff Owen An ASIC design for a high speed implementation of the hash function SHA-256 (384, 512). [Citation Graph (0, 0)][DBLP ] Conf ] Jing Huang , Mariam Momenzadeh , Mehdi Baradaran Tahoori , Fabrizio Lombardi Design and characterization of an and-or-inverter (AOI) gate for QCA implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Ozgur Celebican , Tajana Simunic Rosing , Vincent John Mooney III Energy estimation of peripheral devices in embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Macchiarulo , Consolato F. Caccamo , Davide Pandini A comparison between mask- and field-programmable routing structures on industrial FPGA architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Matteo Monchiero , Gianluca Palermo , Mariagiovanna Sami , Cristina Silvano , Vittorio Zaccaria , Roberto Zafalon Power-aware branch prediction techniques: a compiler-hints based approach for VLIW processors. [Citation Graph (0, 0)][DBLP ] Conf ] Alok A. Katkar , James E. Stine Modified booth truncated multipliers. [Citation Graph (0, 0)][DBLP ] Conf ] Victor V. Zyuban , Sameh W. Asaad , Thomas W. Fox , Anne-Marie Haen , Daniel Littrell , Jaime H. Moreno Design methodology for semi custom processor cores. [Citation Graph (0, 0)][DBLP ] Conf ] Nele Mentens , Siddika Berna Örs , Bart Preneel An FPGA implementation of an elliptic curve processor GF(2m ). [Citation Graph (0, 0)][DBLP ] Conf ] Miguel A. Melgarejo , Carlos Andrés Peña-Reyes Hardware architecture and FPGA implementation of a type-2 fuzzy system. [Citation Graph (0, 0)][DBLP ] Conf ] Zhiyuan Yan , Dilip V. Sarwate High-speed systolic architectures for finite field inversion and division. [Citation Graph (0, 0)][DBLP ] Conf ] 