Conferences in DBLP
Sridhar Narayanan , Rajesh Gupta , Melvin A. Breuer Configuring multiple scan chains for minimum test time. [Citation Graph (0, 0)][DBLP ] Conf ] Pao-Chuan Chen , Bin-Da Liu , Jhing-Fa Wang Overall consideration of scan design and test generation. [Citation Graph (0, 0)][DBLP ] Conf ] Y. H. Choi , T. Jung Configuration of a boundary scan chain for optimal testing of clusters of non boundary scan devices. [Citation Graph (0, 0)][DBLP ] Conf ] Soo Young Lee , Kewal K. Saluja An algorithm to reduce test application time in full scan designs. [Citation Graph (0, 0)][DBLP ] Conf ] Surendra Burman , Chandar Kamalanathan , Naveed A. Sherwani New channel segmentation model and associated routing algorithm for high performance FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Kai Zhu , D. F. Wong On channel segmentation design for row-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Akhilesh Tyagi VLSI design parsing (preliminary version). [Citation Graph (0, 0)][DBLP ] Conf ] Tsung D. Lee , Lawrence P. McNamee Aesthetic routing for transistor schematics. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Francis A tutorial on logic synthesis for lookup-table based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Cong , Yuzheng Ding An optimal technology mapping algorithm for delay optimization in lookup-table based FPGA designs. [Citation Graph (0, 0)][DBLP ] Conf ] Yuji Kukimoto , Masahiro Fujita Rectification method for lookup-table type FPGA's. [Citation Graph (0, 0)][DBLP ] Conf ] Seok-Yoon Kim , Nanda Gopal , Lawrence T. Pillage AWE macromodels of VLSI interconnect for circuit simulation. [Citation Graph (0, 0)][DBLP ] Conf ] J. Eric Bracken , Vivek Raghavan , Ronald A. Rohrer Extension of the asymptotic waveform evaluation technique with the method of characteristics. [Citation Graph (0, 0)][DBLP ] Conf ] M. Murat Alaybeyi , John Y. Lee , Ronald A. Rohrer Numerical integration algorithms and asymptotic waveform evaluation (AWE). [Citation Graph (0, 0)][DBLP ] Conf ] Ashish S. Gadagkar , James R. Armstrong Timing distribution in VHDL behavioral models. [Citation Graph (0, 0)][DBLP ] Conf ] Richard Burch , Farid N. Najm , Ping Yang , Timothy N. Trick McPOWER: a Monte Carlo approach to power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Brand Exhaustive simulation need not require an exponential number of tests. [Citation Graph (0, 0)][DBLP ] Conf ] Alexandre Yakovlev , Luciano Lavagno , Alberto L. Sangiovanni-Vincentelli A unified signal transition graph model for asynchronous control circuit synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Vanbekbergen , Bill Lin , Gert Goossens , Hugo De Man A generalized state assignment theory for transformation on signal transition graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Kuan-Jen Lin , Chen-Shang Lin On the verification of state-coding in STGs. [Citation Graph (0, 0)][DBLP ] Conf ] Thomas G. Szymanski , Narendra V. Shenoy Verifying clock schedules. [Citation Graph (0, 0)][DBLP ] Conf ] Narendra V. Shenoy , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Graph algorithms for clock schedule optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy M. Burks , Karem A. Sakallah , Trevor N. Mudge Identification of critical paths in circuits with level-sensitive latches. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan-Hua Chang , Edward S. Davidson , Karem A. Sakallah Using constraint geometry to determine maximum rate pipeline clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-fuw Lee , Donald T. Tang HIMALAYAS - a hierarchical compaction system with a minimized constraint set. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Varadarajan , Cyrus Bamji Cloning techniques for hierarchical compaction. [Citation Graph (0, 0)][DBLP ] Conf ] Toru Awashima , Wataru Yamamoto , Masao Sato , Tatsuo Ohtsuki An optimal chip compaction method based on shortest path algorithm with automatic jog insertion. [Citation Graph (0, 0)][DBLP ] Conf ] Goro Suzuki , Tetsuya Yamamoto , Kyoji Yuyama , Kotaro Hirasawa MOSAIC: a tile-based datapath layout generator. [Citation Graph (0, 0)][DBLP ] Conf ] Massimiliano Chiodo , Thomas R. Shiple , Alberto L. Sangiovanni-Vincentelli , Robert K. Brayton Automatic compositional minimization in CTL model checking. [Citation Graph (0, 0)][DBLP ] Conf ] Enrico Macii , Bernard Plessier , Fabio Somenzi Verification of systems containing counters. [Citation Graph (0, 0)][DBLP ] Conf ] Filip Van Aelten , Stan Y. Liao , Jonathan Allen , Srinivas Devadas Automatic generation and verification of sufficient correctness properties for synchronous processors. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Devadas , Kurt Keutzer , Sharad Malik , Albert Wang Verification of asynchronous interface circuits with bounded wire delays. [Citation Graph (0, 0)][DBLP ] Conf ] Abdolreza Nabavi-Lishi , Nicholas C. Rumin Delay and bus current evaluation in CMOS logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] F. Rouatbi , Baher Haroun , Asim J. Al-Khalili Power estimation tool for sub-micron CMOS VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Ping-Chung Li , Georgios I. Stamoulis , Ibrahim N. Hajj A probabilistic timing approach to hot-carrier effect estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel G. Saab , Youssef Saab , Jacob A. Abraham CRIS: a test cultivation program for sequential VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Balkrishna Ramkumar , Prithviraj Banerjee Portable parallel test generation for sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rabindra K. Roy , Abhijit Chatterjee , Janak H. Patel , Jacob A. Abraham , Manuel A. d'Abreu Automatic test generation for linear digital systems with bi-level search using matrix transform methods. [Citation Graph (0, 0)][DBLP ] Conf ] Tsing-Fa Lee , Allen C.-H. Wu , Daniel Gajski , Youn-Long Lin An effective methodology for functional pipelining. [Citation Graph (0, 0)][DBLP ] Conf ] Hironori Komi , Shoichiro Yamada , Kunio Fukunaga A scheduling method by stepwise expansion in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Catherine H. Gebotys Optimal synthesis of multichip architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Hsu Chang , Andrew T. Yang Analytic macromodeling and simulation fo tightly-coupled mixed analog-digital circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Feldmann , Robert C. Melville , Shahriar Moinian Automatic differentiation in circuit simulation and device modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Kimon W. Michaels , Andrzej J. Strojwas A methodology for improved circuit simulation efficiency via topology-based variable accuracy device modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Ronn B. Brashear , Douglas R. Holberg , M. Ray Mercer , Lawrence T. Pillage ETA: electrical-level timing analysis. [Citation Graph (0, 0)][DBLP ] Conf ] So-Zen Yao , Nan-Chi Chou , Chung-Kuan Cheng , T. C. Hu An optimal probe testing algorthm for the connectivity verification of MCM substrates. [Citation Graph (0, 0)][DBLP ] Conf ] Gary S. Greenstein , Janak H. Patel E-PROOFS: a CMOS bridging fault simulator. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy On the generation of small dictionaries for fault location. [Citation Graph (0, 0)][DBLP ] Conf ] Uwe Hübner , Heinrich Theodor Vierhaus Efficient partitioning and analysis of digital CMOS-circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wim F. J. Verhaegh , Paul E. R. Lippens , Emile H. L. Aarts , Jan H. M. Korst , Albert van der Werf , Jef L. van Meerbergen Efficiency improvements for force-directed scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Albert van der Werf , M. J. H. Peek , Emile H. L. Aarts , Jef L. van Meerbergen , Paul E. R. Lippens , Wim F. J. Verhaegh Area optimization of multi-functional processing units. [Citation Graph (0, 0)][DBLP ] Conf ] Anantha Chandrakasan , Miodrag Potkonjak , Jan M. Rabaey , Robert W. Brodersen HYPER-LP: a system for power minimization using architectural transformations. [Citation Graph (0, 0)][DBLP ] Conf ] Miodrag Potkonjak , Jan M. Rabaey Maximally fast and arbitrarily fast implementation of linear computations. [Citation Graph (0, 0)][DBLP ] Conf ] Steven J. Seda , Marc G. R. Degrauwe , Wolfgang Fichtner Lazy-expansion symbolic expression approximation in SYNAP. [Citation Graph (0, 0)][DBLP ] Conf ] Francisco V. Fernández , Ángel Rodríguez-Vázquez , J. D. Martín , José L. Huertas Accuate simplification of large symbolic formulae. [Citation Graph (0, 0)][DBLP ] Conf ] Edward W. Y. Liu , Alberto L. Sangiovanni-Vincentelli Behavioral simulation for noise in mixed-mode sampled-data systems. [Citation Graph (0, 0)][DBLP ] Conf ] Allen C.-H. Wu , Tedd Hadley , Daniel Gajski An efficient multi-view design model for real-time interactive synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Roger P. Ang , Nikil D. Dutt Equivalent design representations and transformations for interactive scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Robert C. Armstrong , Jonathan Allen FICOM: a framework for incremental consistency maintenance in multi-representation, structural VLSI databases. [Citation Graph (0, 0)][DBLP ] Conf ] Leon Stok False loops through resource sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Kuehlmann , Reinaldo A. Bergamaschi Timing analysis in high-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Champaka Ramachandran , Fadi J. Kurdahi , Daniel Gajski , Allen C.-H. Wu , Viraphol Chaiyakul Accurate layout area and delay modeling for system level design. [Citation Graph (0, 0)][DBLP ] Conf ] Emily J. Shriver , Karem A. Sakallah Ravel: assigned-delay compiled-code logic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Abdulla Bataineh , Füsun Özgüner , Imre Szauter Parallel logic and fault simulation algorithms for shared memory vector machines. [Citation Graph (0, 0)][DBLP ] Conf ] Naoaki Suganuma , Yukihiro Murata , Satoru Nakata , Shinichi Nagata , Masahiro Tomita , Kotaro Hirano Reconfigurable machine and its application to logic diagnosis. [Citation Graph (0, 0)][DBLP ] Conf ] A. Mahmood , W. I. Baker , Jayantha A. Herath , A. Jayasumana A logic simulation engine based on a modified data flow architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Jiri Soukup Maze router without a grid map. [Citation Graph (0, 0)][DBLP ] Conf ] Mysore Sriram , Sung-Mo Kang Detailed layer assignment for MCM routing. [Citation Graph (0, 0)][DBLP ] Conf ] De-Sheng Chen , Majid Sarrafzadeh A wire-length minimization algorithm for single-layer layouts. [Citation Graph (0, 0)][DBLP ] Conf ] Sujoy Mitra , Sudip Nag , Rob A. Rutenbar , L. Richard Carley System-level routing of mixed-signal ASICs in WREN. [Citation Graph (0, 0)][DBLP ] Conf ] Amelia Shen , Abhijit Ghosh , Srinivas Devadas , Kurt Keutzer On average power dissipation and random pattern testability of CMOS combinational logic networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jerry R. Burch , David E. Long Efficient Boolean function matching. [Citation Graph (0, 0)][DBLP ] Conf ] Kaushik De , Balkrishna Ramkumar , Prithviraj Banerjee ProperSYN: a portable parallel algorithm for logic synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Seh-Woong Jeong , Fabio Somenzi A new algorithm for the binate covering problem and its application to the minimization of Boolean relations. [Citation Graph (0, 0)][DBLP ] Conf ] Lars W. Hagen , Andrew B. Kahng A new approach to effective circuit clustering. [Citation Graph (0, 0)][DBLP ] Conf ] Ching-Wei Yeh , Chung-Kuan Cheng , Ting-Ting Y. Lin A probabilistic multicommodity-flow solution to circuit clustering problems. [Citation Graph (0, 0)][DBLP ] Conf ] L. James Hwang , Abbas El Gamal Optimal replication for min-cut partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Mattan Kamon , Michael J. Tsuk , C. Smithhisler , Jacob White Efficient techniques for inductance extraction of complex 3-D geometries. [Citation Graph (0, 0)][DBLP ] Conf ] Ali El-Zein , Salim Chowdhury An analytical method for finding the maximum crosstalk in lossless-coupled transmission lines. [Citation Graph (0, 0)][DBLP ] Conf ] Sanjay L. Manney , Michel S. Nakhla , Qi-Jun Zhang Time domain analysis of nonuniform frequency dependent high-speed interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen W. Director , Jonathan Allen , J. Duley Engineering education: trends and needs (panel). [Citation Graph (0, 0)][DBLP ] Conf ] Ying-Meng Li , Marwan A. Jabri A zero-skew clock routing scheme for VLSI circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Wasim Khan , Moazzem Hossain , Naveed A. Sherwani Zero skew clock routing in multiple-clock synchronous systems. [Citation Graph (0, 0)][DBLP ] Conf ] Dirk Theune , Ralf Thiele , Thomas Lengauer , Anja Feldmann HERO: hierarchical EMC-constrained routing. [Citation Graph (0, 0)][DBLP ] Conf ] Qing Zhu , Wayne Wei-Ming Dai Perfect-balance planar clock routing with minimal path-length. [Citation Graph (0, 0)][DBLP ] Conf ] Jane S. Sun , Robert W. Brodersen Design of system interface modules. [Citation Graph (0, 0)][DBLP ] Conf ] G. Menez , Michel Auguin , Fernand Boéri , C. Carrière A partitioning algorithm for system-level synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Ross B. Ortega , Gaetano Borriello Synthesis fo the hardware/software interface in microcontroller-based systems. [Citation Graph (0, 0)][DBLP ] Conf ] H. Krämer , J. Müller Assignment of global memory elements for multi-process VHDL specifications. [Citation Graph (0, 0)][DBLP ] Conf ] Sujit Dey , Miodrag Potkonjak , Steven G. Rothweiler Performance optimization of sequential circuits by eliminating retiming bottlenecks. [Citation Graph (0, 0)][DBLP ] Conf ] Pranav Ashar , Sujit Dey , Sharad Malik Exploiting multi-cycle false paths in the performance optimization of sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] William K. C. Lam , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Valid clocking in wavepipelined circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Kimura , Shigemi Kashima , Hiromasa Haneda Precise timing verification of logic circuits under combined delay model. [Citation Graph (0, 0)][DBLP ] Conf ] Elisabeth Kupitz , Jürgen Tacken DECOR - tightly integrated Design Control and Observation. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Bingley , K. Olav ten Bosch , Pieter van der Wolf Incorporating design flow management in a framework based CAD system. [Citation Graph (0, 0)][DBLP ] Conf ] Venu Vasudevan , Yves Mathys , Jim Tolar DAMOCLES: an observer-based approach to design tracking. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Ting Cheng Test generation for delay faults in non-scan and partial scan sequential circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy An efficient non-enumerative method to estimate path delay fault coverage. [Citation Graph (0, 0)][DBLP ] Conf ] Lakshmi N. Reddy , Irith Pomeranz , Sudhakar M. Reddy COMPACTEST-II: a method to generate compact two-pattern test sets for combinational logic circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , David L. Dill Automatic synthesis of 3D asynchronous state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Beerel , Teresa H. Y. Meng Automatic gate-level synthesis of speed-independent circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Venkatesh Akella , Ganesh Gopalakrishnan SHILPA: a high-level synthesis system for self-timed circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Konrad Doll , Frank M. Johannes , Georg Sigl Accurate net models for placement improvement by network flow methods. [Citation Graph (0, 0)][DBLP ] Conf ] Bernd Schürmann , Joachim Altmeyer , Gerhard Zimmermann Three-phase chip planning - an improved top-down chip planning strategy. [Citation Graph (0, 0)][DBLP ] Conf ] Peichen Pan , C. L. Liu Area minimization for general floorplans. [Citation Graph (0, 0)][DBLP ] Conf ] Chung-Hsing Chen , Daniel G. Saab Behavioral synthesis for testability. [Citation Graph (0, 0)][DBLP ] Conf ] Tien-Chien Lee , Wayne Wolf , Niraj K. Jha Behavioral synthesis for easy testability in data path scheduling. [Citation Graph (0, 0)][DBLP ] Conf ] Vivek Chickermane , Jaushin Lee , Janak H. Patel A comparative study of design for testability methods using high-level and gate-level descriptions. [Citation Graph (0, 0)][DBLP ] Conf ] Steven M. Nowick , David L. Dill Exact two-level minimization of hazard-free logic with multiple-input changes. [Citation Graph (0, 0)][DBLP ] Conf ] David S. Kung Hazard-non-increasing gate-level optimization algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] 