Conferences in DBLP
Benjamin W. Wah , Arthur Ieumwananonthachai , Shu Yao , Ting Yu Statistical generalization: theory and applications. [Citation Graph (0, 0)][DBLP ] Conf ] C. Truzzi , Eric Beyne , E. Ringoot , J. Peeters Signal propagation in high-speed MCM circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jimmy Shinn-Hwa Wang , Wayne Wei-Ming Dai Transient analysis of coupled transmission lines characterized with the frequency-dependent losses using scattering-parameter based macromodel. [Citation Graph (0, 0)][DBLP ] Conf ] Junya Kudoh , Toshiro Takahashi , Yukio Umada , Masaharu Kimura , Shigeru Yamamoto , Youichi Ito A CMOS gate array with dynamic-termination GTL I/O circuits. [Citation Graph (0, 0)][DBLP ] Conf ] William F. Richardson , Erik Brunvand Precise exception handling for a self-timed processor. [Citation Graph (0, 0)][DBLP ] Conf ] Mark R. Greenstreet Implementing a STARI chip. [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth Y. Yun , David L. Dill A high-performance asynchronous SCSI controller. [Citation Graph (0, 0)][DBLP ] Conf ] Jean Paul Calvez , Olivier Pasquier Performance assessment of embedded Hw/Sw systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ti-Yen Yen , Wayne Wolf Performance estimation for real-time distributed embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Sérgio Vale Aguiar Campos , Edmund M. Clarke , Wilfredo R. Marrero , Marius Minea Verifying the performance of the PCI local bus using symbolic techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Anand Chavan , Shiu-Kai Chin , Shahid Ikram , Jang Dae Kim , Juin-Yeu Zu Extending VLSI design with higher-order logic. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Wallace , Nirav Dagli , Nader Bagherzadeh Design and implementation of a 100 MHz centralized instruction window for a superscalar microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Kotaro Shimamura , Shigeya Tanaka , Tetsuya Shimomura , Takashi Hotta , Eiki Kamada , Hideo Sawamoto , Teruhisa Shimizu , Kisaburo Nakazawa A superscalar RISC processor with pseudo vector processing feature. [Citation Graph (0, 0)][DBLP ] Conf ] John-David Wellman , Edward S. Davidson The resource conflict methodology for early-stage design space exploration of superscalar RISC processors. [Citation Graph (0, 0)][DBLP ] Conf ] Alexander Dalal , Lavi Lev , Sundari Mitra Design of an efficient power distribution network for the UltraSPARC-I microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] H. Hao , K. Bhabuthmal Clock controller design in SuperSPARC II microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Guillermo Maturana , James L. Ball , Jeffery Gee , Amaresh Iyer , J. Michael O'Connor Incas: a cycle accurate model of UltraSPARC. [Citation Graph (0, 0)][DBLP ] Conf ] Anirudh Devgan Accurate device modeling techniques for efficient timing simulation of integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jay K. Adams , John Alan Miller , Donald E. Thomas Execution-time profiling for multiple-process behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Jainendra Kumar , Noel R. Strader , Jeff Freeman , Michael Miller Emulation verification of the Motorola 68060. [Citation Graph (0, 0)][DBLP ] Conf ] Joan Carletta , Christos A. Papachristou Testability analysis and insertion for RTL circuits based on pseudorandom BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Yu Fang , Alexander Albicki Efficient testability enhancement for combinational circuit. [Citation Graph (0, 0)][DBLP ] Conf ] Indradeep Ghosh , Anand Raghunathan , Niraj K. Jha Design for hierarchical testability of RTL circuits obtained by behavioral synthesis. [Citation Graph (0, 0)][DBLP ] Conf ] Franco Fummi , Donatella Sciuto , M. Serro Synthesis for testability of large complexity controllers. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Montemayor , Marie Sullivan , Jen-Tien Yen , Pete Wilson , Richard Evers , K. R. Kishore The PowerPC 603e microprocessor: an enhanced, low-power, superscalar microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Allen , W. Kurt Lewchuk , J. D. Coddington A high performance bus and cache controller for PowerPC multiprocessing systems. [Citation Graph (0, 0)][DBLP ] Conf ] Charles P. Roth , Frank Levine , Edward H. Welbon Performance monitoring on the PowerPC 604 microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Kai-Yuan Chao , D. F. Wong Thermal placement for high-performance multichip modules. [Citation Graph (0, 0)][DBLP ] Conf ] Glenn Holt , Akhilesh Tyagi EPNR: an energy-efficient automated layout synthesis package. [Citation Graph (0, 0)][DBLP ] Conf ] Vinod Narayananan , David LaPotin , Rajesh K. Gupta , Gopalakrishnan Vijayan PEPPER - a timing driven early floorplanner. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan Connection-oriented net model and fuzzy clustering techniques for K-way circuit partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Tomasz Kozlowski , Erik L. Dagless , Jonathan Saul An enhanced algorithm for the minimization of exclusive-OR sum-of-products for incompletely specified functions. [Citation Graph (0, 0)][DBLP ] Conf ] Timothy Kam , Tiziano Villa , Robert K. Brayton , Alberto L. Sangiovanni-Vincentelli Implicit state minimization of non-deterministic FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Peter A. Franaszek , Christos J. Georgiou , Chung-Sheng Li Adaptive routing in Clos networks. [Citation Graph (0, 0)][DBLP ] Conf ] Luis F. G. Sarmenta , Gill A. Pratt , Stephen A. Ward Rational clocking [digital systems design]. [Citation Graph (0, 0)][DBLP ] Conf ] T. Yokota , H. Matsuoka , K. Okamoto , H. Hirono , A. Hori , S. Sakai A prototype router for the massively parallel computer RWC-1. [Citation Graph (0, 0)][DBLP ] Conf ] Abdel-Fattah Yousif , Jun Gu Concurrent automatic test pattern generation algorithm for combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Irith Pomeranz , Sudhakar M. Reddy Test generation for multiple state-table faults in finite-state machines. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen J. Walsh , John A. Board Pollution control caching. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Yung , Neil C. Wilhelm Caching processor general registers. [Citation Graph (0, 0)][DBLP ] Conf ] Murali Kadiyala , Laxmi N. Bhuyan A dynamic cache sub-block design to reduce false sharing. [Citation Graph (0, 0)][DBLP ] Conf ] Stuart W. Daniel , Jennifer Rexford , James W. Dolter , Kang G. Shin A programmable routing controller for flexible communications in point-to-point networks. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Paul Theis , Lothar Thiele POM: a processor model for image processing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrew Wolfe A case study in low-power system-level design. [Citation Graph (0, 0)][DBLP ] Conf ] Jin Li , Chuan-lin Wu A novel architecture for an ATM switch. [Citation Graph (0, 0)][DBLP ] Conf ] Steven E. Butner , David A. Skirmont Architecture and design of a 40 gigabit per second ATM switch. [Citation Graph (0, 0)][DBLP ] Conf ] Frederik Beeftink , A. J. van Genderen , N. P. van der Meijs Accurate and efficient layout-to-circuit extraction for high-speed MOS and bipolar/BiCMOS integrated circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Jin-Tai Yan An efficient cut-based algorithm on minimizing the number of L-shaped channels for safe routing ordering. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Wen Chang , D. F. Wong , C. K. Wong FPGA global routing based on a new congestion metric. [Citation Graph (0, 0)][DBLP ] Conf ] Bret Stott , Dave Johnson , Venkatesh Akella Asynchronous 2-D discrete cosine transform core processor. [Citation Graph (0, 0)][DBLP ] Conf ] Chin-Long Wey , Haiyan Wang , Cheng-Ping Wang A self-timed redundant-binary number to binary number converter for digital arithmetic processors. [Citation Graph (0, 0)][DBLP ] Conf ] Yao-Wen Chang , D. F. Wong , C. K. Wong Design and analysis of FPGA/FPIC switch modules. [Citation Graph (0, 0)][DBLP ] Conf ] Shashidhar Thakur , D. F. Wong Simultaneous area and delay minimum K-LUT mapping for K-exact networks. [Citation Graph (0, 0)][DBLP ] Conf ] Aigo Lu , Erik L. Dagless , Jonathan M. Saul DART: delay and routability driven technology mapping for LUT based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev Murgai , Masahiro Fujita , Fumiyasu Hirose Logic synthesis for a single large look-up table. [Citation Graph (0, 0)][DBLP ] Conf ] Sudhakar M. Reddy Testing-what's missing? An incomplete list of challenges. [Citation Graph (0, 0)][DBLP ] Conf ] Ivan P. Radivojevic , Forrest Brewer Analysis of conditional resource sharing using a guard-based control representation. [Citation Graph (0, 0)][DBLP ] Conf ] Nelson L. Passos , Edwin Hsing-Mean Sha , Liang-Fang Chao Multi-dimensional interleaving for time-and-memory design optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Srinivas Katkoori , Nand Kumar , Ranga Vemuri High level profiling based low power synthesis technique. [Citation Graph (0, 0)][DBLP ] Conf ] Chuan-Yu Wang , Kaushik Roy Control unit synthesis targeting low-power processors. [Citation Graph (0, 0)][DBLP ] Conf ] Kala Srivatsan , Chaitali Chakrabarti , Lori Lucke Low power data format converter design using semi-static register allocation. [Citation Graph (0, 0)][DBLP ] Conf ] H. Yamada , T. Hotta , T. Nishiyama , F. Murabayashi , T. Yamauchi , H. Sawamoto A 13.3ns double-precision floating-point ALU and multiplier. [Citation Graph (0, 0)][DBLP ] Conf ] Hosahalli R. Srinivas , Keshab K. Parhi A floating point radix 2 shared division/square root chip. [Citation Graph (0, 0)][DBLP ] Conf ] Tzu-Hsi Pan , Hyon-Sok Kay , Youngsun Chun , Chin-Long Wey High-radix SRT division with speculation of quotient digits . [Citation Graph (0, 0)][DBLP ] Conf ] Akihiro Tsutsui , Toshiaki Miyazaki , Kazuhisa Yamada , Naohisa Ohta Special purpose FPGA for high-speed digital telecommunication systems. [Citation Graph (0, 0)][DBLP ] Conf ] Eric Y. Chou , Bing J. Sheu , Tony H. Wu , Robert C. Chang VLSI design of densely-connected array processors. [Citation Graph (0, 0)][DBLP ] Conf ] Santanu Dutta , Wayne Wolf , Andrew Wolfe VLSI issues in memory-system design for video signal processors. [Citation Graph (0, 0)][DBLP ] Conf ] Farnaz Mounes-Toussi , David J. Lilja Write buffer design for cache-coherent shared-memory multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Hung Chi , Siu-Chung Lau Reducing data access penalty using intelligent opcode-driven cache prefetching. [Citation Graph (0, 0)][DBLP ] Conf ] Aaron Goldberg , John A. Trotter Interrupt-based hardware support for profiling memory system performance. [Citation Graph (0, 0)][DBLP ] Conf ] Miriam Leeser , John W. O'Leary Verification of a subtractive radix-2 square root algorithm and implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Yatin Vasant Hoskote , Dinos Moundanos , Jacob A. Abraham Automatic extraction of the control flow machine and application to evaluating coverage of verification vectors. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Cyrluk , Mandayam K. Srivas Theorem proving: not an esoteric diversion, but the unifying framework for industrial verification. [Citation Graph (0, 0)][DBLP ] Conf ] Martin C. Herbordt , Charles C. Weems An empirical study of datapath, memory hierarchy, and network in SIMD array architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Eddy de Greef , Francky Catthoor , Hugo De Man Memory organization for video algorithms on programmable signal processors. [Citation Graph (0, 0)][DBLP ] Conf ] Shigeaki Iwasa , Shung Ho Shing , Hisashi Mogi , Hiroshi Nozuwe , Hiroo Hayashi , Osamu Wakamori , Takashi Ohmizo , Kuninori Tanaka , Hiroshi Sakai , Mitsuo Saito SSM-MP: more scalability in shared-memory multi-processor. [Citation Graph (0, 0)][DBLP ] Conf ] Menghui Zheng , Alexander Albicki Low power and high speed multiplication design through mixed number representations. [Citation Graph (0, 0)][DBLP ] Conf ] Tan-Li Chou , Kaushik Roy Estimation of sequential circuit activity considering spatial and temporal correlations. [Citation Graph (0, 0)][DBLP ] Conf ] Ajay J. Daga , William P. Birmingham A symbolic-simulation approach to the timing verification of interacting FSMs. [Citation Graph (0, 0)][DBLP ] Conf ] Gitanjali Swamy , Robert K. Brayton , Vigyan Singhal Incremental methods for FSM traversal. [Citation Graph (0, 0)][DBLP ] Conf ] Manish Pandey , Alok Jain , Randal E. Bryant , Derek L. Beatty , Gary York , Samir Jain Extraction of finite state machines from transistor netlists by symbolic simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Rolf Drechsler , Bernd Becker Dynamic minimization of OKFDDs. [Citation Graph (0, 0)][DBLP ] Conf ] Minesh B. Amin , Bapiraju Vinnakota Data parallel fault simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Steven Parkes , Prithviraj Banerjee , Janak H. Patel A parallel algorithm for fault simulation based on PROOFS . [Citation Graph (0, 0)][DBLP ] Conf ] Brian Grayson , Saghir A. Shaikh , Stephen A. Szygenda Statistics on concurrent fault and design error simulation. [Citation Graph (0, 0)][DBLP ] Conf ] Michael S. Hsiao , Janak H. Patel A new architectural-level fault simulation using propagation prediction of grouped fault-effects. [Citation Graph (0, 0)][DBLP ] Conf ] Ram K. Krishnamurthy , Ramalingam Sridhar A CMOS wave-pipelined image processor for real-time morphology . [Citation Graph (0, 0)][DBLP ] Conf ] Hyesook Lim , Earl E. Swartzlander Jr. An efficient systolic array for the discrete cosine transform based on prime-factor decomposition . [Citation Graph (0, 0)][DBLP ] Conf ] Abdel Ejnioui , N. Ranganathan Systolic algorithms for tree pattern matching. [Citation Graph (0, 0)][DBLP ] Conf ] Hirendu Vaishnav , Massoud Pedram Logic extraction based on normalized netlengths. [Citation Graph (0, 0)][DBLP ] Conf ] Jimmy Shinn-Hwa Wang , Wayne Wei-Ming Dai Transformation of min-max optimization to least-square estimation and application to interconnect design optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Carragher , Masahiro Fujita , Chung-Kuan Cheng Simple tree-construction heuristics for the fanout problem . [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Yean Hsieh , Wentai Liu , Ralph K. Cavin III , C. Thomas Gray Concurrent timing optimization of latch-based digital systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael J. Schulte , Earl E. Swartzlander Jr. A coprocessor for accurate and reliable numerical computations. [Citation Graph (0, 0)][DBLP ] Conf ] Chantal Ykman-Couvreur , Bill Lin Efficient state assignment framework for asynchronous state graphs. [Citation Graph (0, 0)][DBLP ] Conf ] Stefan Radtke , Jens Bargfrede , Walter Anheier Distributed automatic test pattern generation with a parallel FAN algorithm. [Citation Graph (0, 0)][DBLP ] Conf ] Wai-Chi Fang , Bing J. Sheu , Holger Venus , Rainer Sandau Smart-pixel array processors based on optimal cellular neural networks for space sensor applications. [Citation Graph (0, 0)][DBLP ] Conf ] 