Rudolf Eigenmann Toward a Methodology of Optimizing Programs for High-Performance Computers. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:27-36 [Conf]
Rod Fatoohi Performance Analysis of Four SIMD Machines. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:117-126 [Conf]
P. J. Narayanan Processor Autonomy on SIMD Architectures. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:127-136 [Conf]
Peiyi Tang Exact Side Effects for Interprocedural Dependence Analysis. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:137-146 [Conf]
Gary Sabot, Skef Wholey CMAX: A Fortran Translator for the Connection Machine System. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:147-156 [Conf]
Paul Feautrier Toward Automatic Partitioning of Arrays on Distributed Memory Computers. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:175-184 [Conf]
Thomas Fahringer, Hans P. Zima A Static Parameter Based Performance Prediction Tool for Parallel Programs. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:207-219 [Conf]
Hai-Xiang Lin, Henk J. Sips Parallel Direct Solution of Large Sparse Systems in Finite Element Computations. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:261-270 [Conf]
Xiaodong Zhang Parallel Triangular Decompositions of an Oil Refining Simulation. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:271-280 [Conf]
Arjan J. C. van Gemund Performance Prediction of Parallel Processing Systems: The PAMELA Methodology. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:318-327 [Conf]
Takashi Matsumoto, Kei Hiraki Dynamic Switching of Coherent Cache Protocols and its Effects on Doacross Loops. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:328-337 [Conf]
Koray Öner, Michel Dubois Effects of Memory Latencies on Non-Blocking Processor/Cache Architectures. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:338-347 [Conf]
Hikaru Samukawa A Proposal of Level 3 Interface for Band and Skyline Matrix Factorization Subroutine. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:397-406 [Conf]
Eduard Ayguadé, Jordi Torres Partitioning the Statement per Iteration Space Using Non-Singular Matrices. [Citation Graph (0, 0)][DBLP] International Conference on Supercomputing, 1993, pp:407-415 [Conf]