The SCEAS System
Navigation Menu

Conferences in DBLP

IFIP WG10.3 Publications (ifip10-3)
2004 (conf/ifip10-3/2004dipes)

  1. Chokri Mraidha, Sylvain Robert, Sébastien Gérard, David Servat
    MDA Platform for Complex Embedded Systems Development. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:1-10 [Conf]
  2. Michael Kersten, Wolfgang Nebel
    On Detecting Deadlocks in Large UML Models. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:11-20 [Conf]
  3. Martin Kardos, Yuhong Zhao
    Verification Framework for UML-Based Design of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:21-30 [Conf]
  4. Yuhong Zhao
    LTL's Intutitive Representations and its Automaton Translation. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:31-42 [Conf]
  5. Kazuhiro Ogata, Daigo Yamagishi, Takahiro Seino, Kokichi Futatsugi
    Modeling and Verification of Hybrid Systems Based on Equations. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:43-52 [Conf]
  6. Wojciech Noworyta
    Distribution of Time Interval Between Successive Interrupt Requests. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:53-62 [Conf]
  7. Håkan Sivencrona, Mattias Persson, Jan Torin
    A Membership Agreement Algorithm Detecting and Tolerating Asymmetric Timing Faults. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:63-72 [Conf]
  8. Karen Godary, Isabelle Augé-Blum, Anne Mignotte
    Temporal Bounds for TTA: Validation. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:73-82 [Conf]
  9. Alain Girault, Hamoudi Kalla, Yves Sorel
    An Active Replication Scheme that Tolerates Failure in Distributed Embedded Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:83-92 [Conf]
  10. Uwe Honekamp, Matthias Wernicke
    Development of Distributed Automotive Software: The DaVinci Methodology. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:93-102 [Conf]
  11. Per Johannessen, Fredrik Törner, Jan Torin
    Experiences from Model Based Development of Drive-By-Wire Control Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:103-112 [Conf]
  12. André Luiz de Freitas Francisco, Achim Rettberg, Andreas Hennig
    Hardware Design and Protocol Specification for the Control and Communication within a Mechatronic System. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:113-122 [Conf]
  13. Jean-Paul Jamont, Michel Occello, André Lagrèze
    A Decentralized Self-Organized Approach for Wireless Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:123-132 [Conf]
  14. K. H. (Kane) Kim, C. S. Im, M. C. Kim, Yuqing Li, Seung-Mok Yoo, L. C. Zheng
    A Software Architecture and Supporting Kernel for Largely Synchronously Operating Sensor Networks. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:133-144 [Conf]
  15. Claudia Kretzschmar, Markus Scheithauer, Dietmar Müller
    Adaptive Bus Encoding Schemes for Power-Efficient Data Transfer in DSM Environments. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:145-156 [Conf]
  16. Raimundo S. Barreto, Paulo Romero Martins Maciel, Marília Neves, Eduardo Tavares, Ricardo Massa Ferreira Lima
    A Novel Approach for Off-Line Multiprocesor Scheduling in Embedded Hard Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:157-166 [Conf]
  17. David Doose, Zoubir Mammeri
    Schedulability Analysis and Design of Real-Time Embedded Systems with Partitions. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:167-176 [Conf]
  18. Carsten Boeke, Simon Oberthuer
    Flexible Resource Management - A Framework for Self-Optimizing Real-Time Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:177-186 [Conf]
  19. Carsten Rust, Achim Rettberg
    Automatic Synthesis of SystemC-Code from Formal Specifications. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:187-196 [Conf]
  20. John Hawkins, Ali E. Abdallah
    Hardware Synthesis of a Parallel JPEG Decoder from its Functional Specification. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:197-206 [Conf]
  21. Florian Dittmann, Achim Rettberg
    A Self-Controlled and Dynamically Reconfigurable Architecture. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:207-216 [Conf]
  22. Roman Gumzej, Matjaz Colnaric, Wolfgang A. Halang
    Profiling Specification PEARL Designs. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:217-226 [Conf]
  23. Frank Slomka, Karsten Albers, Richard Hofmann
    A Multiobjective Tabu Search Algorithm for the Design Space Exploration of Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:227-236 [Conf]
  24. Júlio C. B. de Mattos, Lisane B. de Brisolara, Renato Fernandes Hentschke, Luigi Carro, Flávio Rech Wagner
    Design Space Exploration with Automatic Generation of IP-Based Embedded Software. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:237-246 [Conf]
  25. Ricardo Jorge Machado, João M. Fernandes
    A Multi-Level Design Pattern for Embedded Software. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:247-256 [Conf]
  26. Carsten Rust, Franz J. Rammig
    A Petri Net Based Approach for the Design of Dynamically Modifiable Embedded Systems. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:257-266 [Conf]
  27. Brigitte Oesterdiekhoff
    Internet Premium Services for Flexible Format Distributed Services. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:267-276 [Conf]
  28. Lisane B. de Brisolara, Leandro Buss Becker, Luigi Carro, Flávio Rech Wagner, Carlos Eduardo Pereira
    Evaluating High-Level Models for Real-Time Embedded Systems Design. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:277-286 [Conf]
  29. Ashoke Deb
    A Dataflow Language (AVON) as an Architecture Description Language (ADL). [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:287-296 [Conf]
  30. Uwe Glässer, Mona Vajihollahi
    Engineering Concurrent and Reactive Systems with Distributed Real-Time Abstract State Machines. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:297-306 [Conf]
  31. Edgard de Faria Corrêa, Eduardo W. Basso, Gustavo R. Wilke, Flávio Rech Wagner, Luigi Carro
    The Implications of Real-Time Behavior in Networks-on-Chip Architectures. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:307-316 [Conf]
  32. Diogo Zandonai, Sergio Bampi, Marcel Bergerman
    ME64 - A Parallel Hardware Architecture for Motion Estimation Implemented in FPGA. [Citation Graph (0, 0)][DBLP]
    DIPES, 2004, pp:317-326 [Conf]
NOTICE1
System may not be available sometimes or not working properly, since it is still in development with continuous upgrades
NOTICE2
The rankings that are presented on this page should NOT be considered as formal since the citation info is incomplete in DBLP
 
System created by asidirop@csd.auth.gr [http://users.auth.gr/~asidirop/] © 2002
for Data Engineering Laboratory, Department of Informatics, Aristotle University © 2002