Conferences in DBLP
Ivo Bolsens Challenges and Opportunities for FPGA Programmable System Platforms. [Citation Graph (0, 0)][DBLP ] Conf ] Robert Baumann Technology Scaling Trends and Accelerated Testing for Soft Errors in Commercial Silicon Devices. [Citation Graph (0, 0)][DBLP ] Conf ] Yi Zhao , Sujit Dey Separate Dual-Transistor Registers - A Circuit Solution for On-line Testing of Transient Error in UDSM-IC. [Citation Graph (0, 0)][DBLP ] Conf ] Y. Tsiatouhas , S. Matakias , Angela Arapoyanni , Th. Haniotakis A Sense Amplifier Based Circuit for Concurrent Detection of Soft and Timing Errors in CMOS ICs. [Citation Graph (0, 0)][DBLP ] Conf ] Whitney J. Townsend , Jacob A. Abraham , Parag K. Lala On-Line Error Detecting Constant Delay Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Vitalij Ocheretnij , Michael Gössel , Egor S. Sogomonyan , Daniel Marienfeld A Modulo p Checked Self-Checking Carry Select Adder. [Citation Graph (0, 0)][DBLP ] Conf ] Petros Oikonomakos , Mark Zwolinski Foundation of Combined Datapath and Controller Self-checking Design. [Citation Graph (0, 0)][DBLP ] Conf ] Kartik Mohanram , Egor S. Sogomonyan , Michael Gössel , Nur A. Touba Synthesis of Low-Cost Parity-Based Partially Self-Checking Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Steffen Tarnick A Design Method for Embedded Self-Testing t-UED and BUED Code Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] A. Matrosova , Vladimir Ostrovsky , Ilya Levin , K. Nikitin Designing FPGA based Self-Testing Checkers for m-out-of-n Codes. [Citation Graph (0, 0)][DBLP ] Conf ] Haralampos-G. D. Stratigopoulos , Yiorgos Makris An Analog Checker With Input-Relative Tolerance for Duplicate Signals. [Citation Graph (0, 0)][DBLP ] Conf ] Daniele Rossi , V. E. S. van Dijk , Richard P. Kleihorst , André K. Nieuwland , Cecilia Metra Power Consumption of Fault Tolerant Codes: the Active Elements. [Citation Graph (0, 0)][DBLP ] Conf ] Joakim Aidemark , Peter Folkesson , Johan Karlsson On the Probability of Detecting Data Errors Generated by Permanent Faults Using Time Redundancy. [Citation Graph (0, 0)][DBLP ] Conf ] André K. Nieuwland , Richard P. Kleihorst The positive effect on IC yield of embedded Fault Tolerance for SEUs. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad A. Naal , Emmanuel Simeu , Salvador Mir On-Line Testable Decimation Filter Design for AMS Systems. [Citation Graph (0, 0)][DBLP ] Conf ] D. G. Nikolos , Dimitris Nikolos , Haridimos T. Vergos , Costas Efstathiou An Efficient BIST scheme for High-Speed Adders. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Nicolaidis , Nadir Achouri , Lorena Anghel Memory Built-In Self-Repair for Nanotechnologies. [Citation Graph (0, 0)][DBLP ] Conf ] Matteo Sonza Reorda , Massimo Violante Accurate and Efficient Analysis of Single Event Transients in VLSI Circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Chaowen Yu , Wei Li , Sudhakar M. Reddy , Irith Pomeranz An Improved Markov Source Design for Scan BIST. [Citation Graph (0, 0)][DBLP ] Conf ] Martin Omaña , Giacinto Papasso , Daniele Rossi , Cecilia Metra A Model for Transient Fault Propagation in Combinatorial Logic. [Citation Graph (0, 0)][DBLP ] Conf ] Massimo Violante , M. Ceschia , Matteo Sonza Reorda , A. Paccagnella , Paolo Bernardi , Maurizio Rebaudengo , D. Bortolato , M. Bellato , P. Zambolin , A. Candelori Analyzing SEU Effects in SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Patrick Girard , Olivier Héron , Serge Pravossoudovitch , Michel Renovell Defect Analysis for Delay-Fault BIST in FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Sergio D'Angelo , M. Mancini , Giacomo R. Sechi A Fault Injection Tool for SRAM-based FPGAs. [Citation Graph (0, 0)][DBLP ] Conf ] Rajesh Venkatasubramanian , John P. Hayes , Brian T. Murray Low-Cost On-Line Fault Detection Using Control Flow Assertions. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto A Watchdog Processor to Detect Data and Control Flow Errors. [Citation Graph (0, 0)][DBLP ] Conf ] George Xenoulis , Dimitris Gizopoulos , Nektarios Kranitis , Antonis M. Paschalis Low-Cost, On-Line Software-Based Self-Testing of Embedded Processor Cores. [Citation Graph (0, 0)][DBLP ] Conf ] Sobeeh Almukhaizim , Petros Drineas , Yiorgos Makris On Compaction-Based Concurrent Error Detection. [Citation Graph (0, 0)][DBLP ] Conf ] Victor Varshavsky , Ilya Levin , Vladimir Ostrovsky Increasing Implementability of beta-driven Threshold Checkers. [Citation Graph (0, 0)][DBLP ] Conf ] O. Goloubeva , Matteo Sonza Reorda , Massimo Violante An RT-level Concurrent Error Detection Technique for Data Dominated Systems. [Citation Graph (0, 0)][DBLP ] Conf ] Alfredo Benso , Stefano Di Carlo , Giorgio Di Natale , Paolo Prinetto , I. Solcia , Luca Tagliaferri FAUST: FAUlt-injection Script-based Tool. [Citation Graph (0, 0)][DBLP ] Conf ] S. R. Seward , Parag K. Lala Fault Injection in Digital Logic Circuits at the VHDL Level. [Citation Graph (0, 0)][DBLP ] Conf ] Monica Alderighi , Fabio Casini , Sergio D'Angelo , F. Faure , M. Mancini , S. Pastore , Giacomo R. Sechi , Raoul Velazco Radiation test methodology for SRAM-based FPGAs by using THESIC. [Citation Graph (0, 0)][DBLP ] Conf ] Fabian Vargas , Diogo B. Brum , Dárcio Prestes , Leticia Maria Veiras Bolzani , E. Rhod , Matteo Sonza Reorda Introducing SW-Based Fault Handling Mechanisms to Cope with EMI in Embedded Electronics: Are They A Good Remedy? [Citation Graph (0, 0)][DBLP ] Conf ] Fernando M. Gonçalves , Marcelino B. Santos , Isabel C. Teixeira , João Paulo Teixeira Property Coverage for Quality Assessment of Fault Tolerant or Fail Safe Systems. [Citation Graph (0, 0)][DBLP ] Conf ] N. Venkateswaran , V. Balaji , V. Mahalingam , T. L. Rajaprabhu Analysis of Bit Transition Count for EDAC Encoded FSM. [Citation Graph (0, 0)][DBLP ] Conf ] Rodrigo Picos , Joan Font , Eugeni Isern , Miquel Roca , Eugenio García A Configurable Built in Current Sensor for Mixed Signal Circuit Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Andrzej Krasniewski Evaluation of the Quality of Testing Path Delay Faults under Restricted Input Assumption. [Citation Graph (0, 0)][DBLP ] Conf ] Matthias Pflanz , Heinrich Theodor Vierhaus Control Signal Protection For High Performance Processors. [Citation Graph (0, 0)][DBLP ] Conf ] B. Alorda , Jaume Segura An Evaluation of Built-in vs. Off-chip Strategies for On-line Transient Current Testing. [Citation Graph (0, 0)][DBLP ] Conf ] Christian Galke , Marcus Grabow , Heinrich Theodor Vierhaus Perspectives of Combining on-line and off-line Test Technology for Dependable Systems on a Chip. [Citation Graph (0, 0)][DBLP ] Conf ] Elmar Dilger , Matthias Gulbins , Thomas Ohnesorge , Bernd Straube On a Redundant Diversified Steering Angle. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto Manzone , Claudio Genta Automatic toolset for fault tolerant design: results demonstration on a running industrial application. [Citation Graph (0, 0)][DBLP ] Conf ] D. J. Beauregard , Zbigniew Kalbarczyk , Ravishankar K. Iyer , Savio N. Chau , Leon Alkalai Error-Injection-Based Failure Characterization of the IEEE 1394 Bus. [Citation Graph (0, 0)][DBLP ] Conf ] Raoul Velazco , Lorena Anghel , S. Saleh A Methodology for Test Replacement Solutions of Obsolete Processors. [Citation Graph (0, 0)][DBLP ] Conf ] L. Di Silvio , Daniele Rossi , Cecilia Metra Crosstalk Effect Minimization for Encoded Busses. [Citation Graph (0, 0)][DBLP ] Conf ] Dimitri Kagaris , Spyros Tragoudas InTeRail: Using Existing and Extra Interconnects to Test Core-Based SOCs. [Citation Graph (0, 0)][DBLP ] Conf ] 