Conferences in DBLP
Maurice V. Wilkes Size, Power, and Speed [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang K. Giloi Towards a Taxonomy of Computer Architecture Based on the Machine Data Type View [Citation Graph (1, 0)][DBLP ] Conf ] Algirdas Avizienis Frameworks for a Taxonomy of Fault-Tolerance Attributes in Computer Systems [Citation Graph (0, 0)][DBLP ] Conf ] Björn Pehrson , Joachim Parrow Caddie - An Interactive Design Environment [Citation Graph (0, 0)][DBLP ] Conf ] Subrata Dasgupta On the Verification of Computer Architectures Using an Architecture Description Language [Citation Graph (0, 0)][DBLP ] Conf ] Richard M. King Research on Synthesis of Concurrent Computing Systems [Citation Graph (0, 0)][DBLP ] Conf ] Allan L. Fisher , H. T. Kung , Louis Monier , Yasunori Dohi Architecture of the PSC: A Programmable Systolic Chip [Citation Graph (0, 0)][DBLP ] Conf ] Allan L. Fisher , H. T. Kung Synchronizing Large VLSI Processor Arrays [Citation Graph (0, 0)][DBLP ] Conf ] Robert A. Wagner The Boolean Vector Machine [BVM] [Citation Graph (0, 0)][DBLP ] Conf ] Maurizio A. Bonuccelli , Elena Lodi , Fabrizio Luccio , Piero Maestrini , Linda Pagli A VLSI Tree Machine for Relational Data Bases [Citation Graph (0, 0)][DBLP ] Conf ] L. J. Caluwaerts , J. Debacker , J. A. Peperstraete Implementing Streams on a Data Flow Computer System With Paged Memory [Citation Graph (0, 0)][DBLP ] Conf ] Joseph E. Requa The Piecewise Data Flow Architecture Control Flow and Register Management [Citation Graph (0, 0)][DBLP ] Conf ] Mario Tokoro , J. R. Jagannathan , Hideki Sunahara On the Working Set Concept for Data-Flow Machines [Citation Graph (0, 0)][DBLP ] Conf ] R. W. Marczynski , J. Milewski A Data Driven System Based on a Microprogrammed Processor Module [Citation Graph (0, 0)][DBLP ] Conf ] David A. Patterson , Phil Garrison , Mark D. Hill , Dimitris Lioupis , Chris Nyberg , Tim Sippel , Korbin Van Dyke Architecture of a VLSI Instruction Cache for a RISC [Citation Graph (0, 0)][DBLP ] Conf ] Phil C. C. Yeh , Janak H. Patel , Edward S. Davidson Performance of Shared Cache for Parallel-Pipelined Computer Systems [Citation Graph (0, 0)][DBLP ] Conf ] James R. Goodman Using Cache Memory to Reduce Processor-Memory Traffic [Citation Graph (1, 0)][DBLP ] Conf ] James E. Smith , James R. Goodman A Study of Instruction Cache Organizations and Replacement Policies [Citation Graph (0, 0)][DBLP ] Conf ] Joseph A. Fisher Very Long Instruction Word Architectures and the ELI-512 [Citation Graph (0, 0)][DBLP ] Conf ] Shinji Tomita , Kiyoshi Shibayama , Toshiaki Kitamura , Toshiyuki Nakata , Hiroshi Hagiwara A User-Microprogrammable, Local Host Computer With Low-Level Parallelism [Citation Graph (0, 0)][DBLP ] Conf ] Richard H. Gumpertz Combining Tags With Error Codes [Citation Graph (0, 0)][DBLP ] Conf ] Young Gil Park , Jung Wan Cho Fault Diagnosis of Bit-Slice Processor [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Angel Fiol , Ignacio Alegre , J. Luis A. Yebra Line Digraph Iterations and the (d,k) Problem for Directed Graphs [Citation Graph (0, 0)][DBLP ] Conf ] Eli Opper , Miroslaw Malek , G. Jack Lipovski Resource Allocation in Rectangular CC-Banyans [Citation Graph (0, 0)][DBLP ] Conf ] Frantisek Sovis Uniform Theory of the Shuffle-Exchange Type Permutation Networks [Citation Graph (0, 0)][DBLP ] Conf ] Vason P. Srini , Jorge F. Asenjo Analysis of Cray-1S Architecture [Citation Graph (0, 0)][DBLP ] Conf ] Harry F. Jordan Performance Measurements on HEP - A Pipelined MIMD Computer [Citation Graph (0, 0)][DBLP ] Conf ] Hideharu Amano , Takaichi Yoshida , Hideo Aiso (SM)2: Sparse Matrix Solving Machine [Citation Graph (0, 0)][DBLP ] Conf ] R. Kalyana Krishnan , A. K. Rajasekar , C. S. Moghe An Experimental System for Computer Science Instruction [Citation Graph (0, 0)][DBLP ] Conf ] Klaus Kronlof Execution Control and Memory Management of a Data Flow Signal Processor [Citation Graph (0, 0)][DBLP ] Conf ] Masasuke Kishi , Hiroshi Yasuhara , Yasusuke Kawamura DDDP: A Distributed Data Driven Processor [Citation Graph (0, 0)][DBLP ] Conf ] Naohisa Takahashi , Makoto Amamiya A Data Flow Processor Array System: Design and Analysis [Citation Graph (0, 0)][DBLP ] Conf ] Kenneth A. Pier A Retrospective on the Dorado, A High-Performance Personal Computer [Citation Graph (0, 0)][DBLP ] Conf ] Robert J. Dugan System/370 Extended Architecture: A Program View of the Channel Subsystem [Citation Graph (0, 0)][DBLP ] Conf ] Richard L. Norton , Jacob A. Abraham Adaptive Interpretation as a Means of Exploiting Complex Instruction Sets [Citation Graph (0, 0)][DBLP ] Conf ] Manoj Kumar , Daniel M. Dias , J. Robert Jump Switching Strategies in a Class of Packet Switching Networks [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin W. Wah A Comparative Study of Distributed Resource Sharing on Multiprocessors [Citation Graph (0, 0)][DBLP ] Conf ] W. Kent Fuchs , Jacob A. Abraham , Kuang-Hua Huang Concurrent Error Detection in VLSI Interconnection Networks [Citation Graph (0, 0)][DBLP ] Conf ] Wolfgang K. Giloi , Peter M. Behr Hierarchical Function Distribution - A Design Principle for Advanced Multicomputer Architectures [Citation Graph (0, 0)][DBLP ] Conf ] Luigi Stringa EMMA: An Industrial Experience on Large Multiprocessing Architectures [Citation Graph (0, 0)][DBLP ] Conf ] Lars Philipson , Bo Nilsson , Bjorn Breidegard A Communication Structure for a Multiprocessor Computer with Distributed Global Memory [Citation Graph (0, 0)][DBLP ] Conf ] Hiromu Hayashi , Akira Hattori , Haruo Akimoto ALPHA: A High-Performance LISP Machine Equipped with a New Stack Structure and Garbage Collection System [Citation Graph (1, 0)][DBLP ] Conf ] Shinji Umeyama , Koichiro Tamura A Parallel Execution Model of Logic Programs [Citation Graph (0, 0)][DBLP ] Conf ] Claudia Schmittgen , Werner E. Kluge A System Architecture for the Concurrent Evaluation of Applicative Program Expressions [Citation Graph (0, 0)][DBLP ] Conf ] Yoshinori Yamaguchi , Kenji Toda , Toshitsugu Yuba A Performance Evaluation of a Lisp-Based Data-Driven Machine (EM-3) [Citation Graph (0, 0)][DBLP ] Conf ] Gerard Gaillat The Design of a Parallel Processor for Image Processing On-Board Satellites: An Application Oriented Approach [Citation Graph (0, 0)][DBLP ] Conf ] Steven L. Tanimoto A Pyramidal Approach to Parallel Processing [Citation Graph (0, 0)][DBLP ] Conf ] Hitoshi Nishimura , Hiroshi Ohno , Toru Kawata , Isao Shirakawa , Koichi Omura LINKS-1: A Parallel Pipelined Multimicrocomputer System for Image Creation [Citation Graph (0, 0)][DBLP ] Conf ] T. Ericsson , P. E. Danielsson LIPP-A SIMD Multiprocessor Architecture for Image Processing [Citation Graph (0, 0)][DBLP ] Conf ] Philip C. Treleaven The New Generation of Computer Architecture [Citation Graph (0, 0)][DBLP ] Conf ] Shunichi Uchida Inference Machine: From Sequential to Paralle [Citation Graph (0, 0)][DBLP ] Conf ] Tohru Moto-Oka Overview to the Fifth Generation Computer System Project [Citation Graph (0, 0)][DBLP ] Conf ] Kunio Murakami , Takeo Kakuta , Nobuyoshi Miyazaki , Shigeki Shibayama , Haruo Yokota A Relational Data Base Machine: First Step to Knowledge Base Machine [Citation Graph (1, 0)][DBLP ] Conf ] Arvind , Robert A. Iannucci A Critique of Multiprocessing von Neumann Style [Citation Graph (0, 0)][DBLP ] Conf ] 