Conferences in DBLP
Forbes J. Burkowski A Vector and Array Multiprocessor Extension of the Sylvan Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Alejandro A. Kapauan , J. Timothy Field , Dennis Gannon , Lawrence Snyder The Pringle Parallel Computer. [Citation Graph (0, 0)][DBLP ] Conf ] Mehrad Yasrebi , G. Jack Lipovski A State-of-the-Art SIMD Two-Dimensional FFT Array Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Y.-W. Ma , R. Krishnamurti The Architecture of REPLICA-A Special-Purpose Computer System for Active Multi-Sensory Perception of 3-Dimensional Objects. [Citation Graph (0, 0)][DBLP ] Conf ] Samuel M. Goldwasser A Generalized Object Display Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Katsura Kawakami , Shigeo Shimazaki A Special Purpose LSI Processor Using the DDA Algorithm for Image Transformation. [Citation Graph (0, 0)][DBLP ] Conf ] Benjamin W. Wah , Guo-Jie Li , Chee Fen Yu The Status of MANIP-A Multicomputer Architecture for Solving Combinatorial Extremum-Search Problems. [Citation Graph (0, 0)][DBLP ] Conf ] Rubén González-Rubio , J. Rohmer , D. Terral The Schuss Filter: A Processor for Non-Numerical Data Processing. [Citation Graph (1, 0)][DBLP ] Conf ] Carl Ebeling , Andrew J. Palay The Design and Implementation of a VLSI Chess Move Generator. [Citation Graph (0, 0)][DBLP ] Conf ] Manjai Lee , Chuan-lin Wu Performance Analysis of Circuit Switching Baseline Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Clyde P. Kruskal , Marc Snir The Importance of Being Square. [Citation Graph (0, 0)][DBLP ] Conf ] Chi-Yuan Chin , Kai Hwang Connection Principles for Multipath Packet Switching Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss , James E. Smith Instruction Issue Logic for Pipelined Supercomputers. [Citation Graph (0, 0)][DBLP ] Conf ] Robert G. Wedig , Marc A. Rose The Reduction of Branch Instruction Execution Overhead Using Structured Control Flow. [Citation Graph (0, 0)][DBLP ] Conf ] Utpal Banerjee , Daniel Gajski Fast Execution of Loops With IF Statements. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Gajski , Won Kim , Shinya Fushimi A Parallel Pipelined Relational Query Processor: An Architectural Overview. [Citation Graph (2, 0)][DBLP ] Conf ] Arun K. Somani , Vinod K. Agarwal An Efficient VLSI Dictionary Machine. [Citation Graph (1, 0)][DBLP ] Conf ] Allan L. Fisher Dictionary Machines With a Small Number of Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Mark D. Hill , Alan Jay Smith Experimental Evaluation of On-Chip Microprocessor Cache Memories. [Citation Graph (0, 0)][DBLP ] Conf ] James R. Goodman , MenChow Chiang The Use of Static Column RAM as a Memory Hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Yutaka Ishikawa , Mario Tokoro The Design of an Object Oriented Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] David Ungar , Ricki Blau , Peter Foley , A. Dain Samples , David A. Patterson Architecture of SOAR: Smalltalk on a RISC. [Citation Graph (0, 0)][DBLP ] Conf ] Pradip Bose , Edward S. Davidson Design of Instruction Set Architectures for Support of High-Level Languages . [Citation Graph (0, 0)][DBLP ] Conf ] Patrice Quinton Automatic Synthesis of Systolic Arrays from Uniform Recurrent Equations. [Citation Graph (0, 0)][DBLP ] Conf ] Chang Nian Zhang , David Y. Y. Yun Multi-Dimensional Systolic Networks for Discrete Fourier Transform. [Citation Graph (0, 0)][DBLP ] Conf ] José A. B. Fortes , Dan I. Moldovan Data Broadcasting in Linearly Scheduled Array Processors. [Citation Graph (0, 0)][DBLP ] Conf ] I. V. Ramakrishnan , Peter J. Varman Modular Matrix Multiplication on a Linear Array. [Citation Graph (0, 0)][DBLP ] Conf ] T. R. N. Rao Joint Encryption and Error Correction Schemes. [Citation Graph (0, 0)][DBLP ] Conf ] Bella Bose Unidirectional Error Correction/Detection for VLSI Memory. [Citation Graph (0, 0)][DBLP ] Conf ] C. L. Chen Error-Correcting Codes for Semiconductor Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Khaled A. S. Abdel-Ghaffar , Robert J. McEliece Soft Error Correction for Increased Densities in VLSI Memories. [Citation Graph (0, 0)][DBLP ] Conf ] Richard M. King , Robert A. Wagner Combining Speed with Alpha-Particle Induced Memory Error Tolerance in a Large Boolean Vector Machine (Extended Abstract). [Citation Graph (0, 0)][DBLP ] Conf ] Laxmi N. Bhuyan On the Performance of Loosely Coupled Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ravi Mehrotra , Sarosh Talukdar Scheduling of Tasks for Distributed Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Krishna M. Kavi , Edward W. Banios Message Repository Definitional Facility: An Architectural Model for Interprocess Communication. [Citation Graph (0, 0)][DBLP ] Conf ] Prithviraj Banerjee , Jacob A. Abraham Fault-Secure Algorithms for Multiple-Processor Systems. [Citation Graph (1, 0)][DBLP ] Conf ] Lubomir Bic Execution of Logic Programs on a Dataflow Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Walter G. Rudd , Duncan A. Buell , Donald M. Chiarulli A High Performance Factoring Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Joel S. Emer , Douglas W. Clark A Characterization of Processor Performance in the VAX-11/780. [Citation Graph (0, 0)][DBLP ] Conf ] Wolf-Dietrich Moeller , Gerd Sandweg The Peripheral Processor PP4 - A Highly Regular VLSI Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Lars Philipson VLSI Based Design Principles for MIMD Multiprocessor Computers with Distributed Memory Management. [Citation Graph (0, 0)][DBLP ] Conf ] Maheswara R. Samatham Dhiraj K. Pradhan: A Multiprocessor Network Suitable for Single-Chip VLSI Implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Larry Rudolph , Zary Segall Dynamic Decentralized Cache Schemes for MIMD Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Mark S. Papamarcos , Janak H. Patel A Low-Overhead Coherence Solution for Multiprocessors with Private Cache Memories. [Citation Graph (0, 0)][DBLP ] Conf ] James K. Archibald , Jean-Loup Baer An Economical Solution to the Cache Coherence Problem. [Citation Graph (0, 0)][DBLP ] Conf ] Ilkka J. Haikala Cache Hit Ratios With Geometric Task Switch Intervals. [Citation Graph (0, 0)][DBLP ] Conf ] 