Conferences in DBLP
Susan J. Eggers , Randy H. Katz Evaluating the Performance of Four Snooping Cache Coherency Protocols. [Citation Graph (1, 0)][DBLP ] Conf ] David R. Cheriton , Hendrik A. Goosen , Patrick D. Boyle Multi-level Shared Caching Techniques for Scalability in VMP-M/C. [Citation Graph (0, 0)][DBLP ] Conf ] Atsuhiro Goto , Akira Matsumoto , Evan Tick Design and Performance of a Coherent Cache for Parallel Logic Programming Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] V. G. Grafe , G. S. Davidson , J. E. Hoch , V. P. Holmes The Epsilon Dataflow Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Shuichi Sakai , Yoshinori Yamaguchi , Kei Hiraki , Yuetsu Kodama , Toshitsugu Yuba An Architecture of a Dataflow Single Chip Processor. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Nitezki Exploiting Data Parallelism in Signal Processing on a Data Flow Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Roland N. Ibbett , T. M. Hopkins , K. I. M. McKinnon Architectural Mechanisms to Support Sparse Vector Processing. [Citation Graph (0, 0)][DBLP ] Conf ] David T. Harper III , Darel A. Linebarger A Dynamic Storage Scheme for Conflict-Free Vector Access. [Citation Graph (0, 0)][DBLP ] Conf ] Kazuaki Murakami , Naohiko Irie , Morihiro Kuga , Shinji Tomita SIMP (Single Instruction stream/Multiple Instruction Pipelining): A Novel High-Speed Single-Processor Architecture. [Citation Graph (0, 0)][DBLP ] Conf ] Yosi Ben-Asher , David Egozi , Assaf Schuster 2-D SIMD Algorithms in the Perfect Shuffle Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Miguel Valero-García , Juan J. Navarro , José M. Llabería , Mateo Valero Systematic Hardware Adaptation of Systolic Algorithms. [Citation Graph (0, 0)][DBLP ] Conf ] Ming-Syan Chen , Kang G. Shin Task Migration in Hypercube Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Steven A. Przybylski , Mark Horowitz , John L. Hennessy Characteristics of Performance-Optimal Multi-Level Cache Hierarchies. [Citation Graph (0, 0)][DBLP ] Conf ] David A. Wood , Randy H. Katz Supporting Reference and Dirty Bits in SPUR's Virtual Address Cache. [Citation Graph (0, 0)][DBLP ] Conf ] Richard E. Kessler , Richard Jooss , Alvin R. Lebeck , Mark D. Hill Inexpensive Implementations of Set-Associativity. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-Hann Wang , Jean-Loup Baer , Henry M. Levy Organization and Performance of a Two-Level Virtual-Real Cache Hierarchy. [Citation Graph (0, 0)][DBLP ] Conf ] Chris R. Jesshope , P. R. Miller , Jay T. Yantchev High Performance Communications in Processor Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Haim E. Mizrahi , Jean-Loup Baer , Edward D. Lazowska , John Zahorjan Introducing Memory into Switch Elements of Multiprocessor Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Steven L. Scott , Gurindar S. Sohi Using Feedback to Control Tree Saturation in Multistage Interconnection Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Paul D. Ezhilchelvan , Santosh K. Shrivastava , Alan Tully Constructing Replicated Systems Using Processors with Point-to-Point Communication Links. [Citation Graph (0, 0)][DBLP ] Conf ] Hans Benker , Jean-Michel Beacco , Sylvie Bescos , Michel Dorochevsky , Thomas Jeffré , Anita Pohlmann , Jacques Noyé , Bruno Poterie , Alan P. Sexton , Jean-Claude Syre , Oliver Thibault , Günter Watzlawik KCM: A Knowledge Crunching Machine. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok Singhal , Yale N. Patt A High Performance Prolog Processor with Multiple Function Units. [Citation Graph (0, 0)][DBLP ] Conf ] M. Morioka S. Yamaguchi, T. Bandoh: Evaluation of Memory System for Integrated Prolog Processor IPP. [Citation Graph (0, 0)][DBLP ] Conf ] Kam-Fai Wong , M. Howard Williams A Type Driven Hardware Engine for Prolog Clause Retrieval over a Large Knowledge Base. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-mei W. Hwu , Thomas M. Conte , Pohua P. Chang Comparing Software and Hardware Schemes For Reducing the Cost of Branches. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew K. Farrens , Andrew R. Pleszkun Improving Performance of Small On-Chip Instruction Caches. [Citation Graph (0, 0)][DBLP ] Conf ] Wen-mei W. Hwu , Pohua P. Chang Achieving High Instruction Cache Performance with an Optimizing Compiler. [Citation Graph (0, 0)][DBLP ] Conf ] Peter Steenkiste The Impact of Code Density on Instruction Cache Performance. [Citation Graph (0, 0)][DBLP ] Conf ] Rishiyur S. Nikhil Can Dataflow Subsume von Neumann Computing? [Citation Graph (0, 0)][DBLP ] Conf ] Wolf-Dietrich Weber , Anoop Gupta Exploring the Benefits of Multiple Hardware Contexts in a Multiprocessor Architecture: Preliminary Results. [Citation Graph (0, 0)][DBLP ] Conf ] Norman P. Jouppi Architectural and Organizational Tradeoffs in the Design of the MultiTitan CPU. [Citation Graph (0, 0)][DBLP ] Conf ] Mitsuhisa Sato , Shuichi Ichikawa , Eiichi Goto Run-Time Checking in Lisp by Integrating Memory Addressing and Range Checking. [Citation Graph (0, 0)][DBLP ] Conf ] Andy Hopper , Alan Jones , Dimitris Lioupis Multiple vs. Wide Shared Bus Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Annaratone , Roland Rühl Performance Measurements on a Commercial Multiprocessor Running Parallel Code. [Citation Graph (0, 0)][DBLP ] Conf ] Marco Annaratone , Claude Pommerell , Roland Rühl Interprocessor Communication Speed and Performance in Distributed-memory Parallel Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Dipak Ghosal , Satish K. Tripathi , Laxmi N. Bhuyan , Hong Jiang Analysis of Computation-Communication Issues in Dynamic Dataflow Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Saul A. Kravitz , Randal E. Bryant , Rob A. Rutenbar Logic Simulation on Massively Parallel Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Tomoo Fukazawa , Takashi Kimura , Masaaki Tomizawa , Kazumitsu Takeda , Yoshitaka Itoh R256: A Research Parallel Processor for Scientific Computation. [Citation Graph (0, 0)][DBLP ] Conf ] Manuel L. Anido , D. J. Allerton , Ed Zaluska A Three-Port/Three-Access Register File for Concurrent Processing and I/O Communication in a RISC-Like Graphics Engine. [Citation Graph (0, 0)][DBLP ] Conf ] J. M. Mulder , R. J. Portier , A. Srivastava , R. in 't Velt An Architecture Framework for Application-Specific and Scalable Architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Kichul Kim , Viktor K. Prasanna Perfect Latin Squares and Parallel Array Access. [Citation Graph (0, 0)][DBLP ] Conf ] Shlomo Weiss An Aperiodic Storage Scheme to Reduce Memory Conflicts in Vector Processors. [Citation Graph (0, 0)][DBLP ] Conf ] Chuen-Liang Chen , Chung-Kai Liao Analysis of Vector Access Performance on Skewed Interleaved Memory. [Citation Graph (0, 0)][DBLP ] Conf ] Anant Agarwal , Mathews Cherian Adaptive Backoff Synchronization Techniques. [Citation Graph (0, 0)][DBLP ] Conf ] Per Stenström A Cache Consistency Protocol for Multiprocessors with Multistage Networks. [Citation Graph (0, 0)][DBLP ] Conf ] Hong-Men Su , Pen-Chung Yew On Data Synchronization for Multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] 