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Conferences in DBLP

IEEE International Symposium on Circuits and Systems (ISCAS) (iscas)
2001 (conf/iscas/2001)

  1. S. W. Ng, Y. S. Lee
    Small signal simulation of resonant converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:1-4 [Conf]
  2. Wen-Li Lee, Yung-Chang Chen, Kao-Sheng Hsieh
    Ultrasonic liver tissues classification by fractal feature vector based on M-band wavelet transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:1-4 [Conf]
  3. Antônio Carlos M. de Queiroz
    Unbalanced lattice switched-current filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:1-4 [Conf]
  4. Seung-Moon Yoo, Seong-Ook Jung, Sung-Mo Kang
    Low cost and high efficiency BIST scheme with 2-level LFSR and ATPT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:1-4 [Conf]
  5. Keishi Chikamura, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    IEEE1394 system simulation environment and a design of its link layer controller. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:1-4 [Conf]
  6. S. Masupe, T. Arslan
    Low power order based DCT processing algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:5-8 [Conf]
  7. B. Pankiewicz, M. Wojcikowski, Stanislaw Szczepanski, Yichuang Sun
    A CMOS field programmable analog array and its application in continuous-time OTA-C filter design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:5-8 [Conf]
  8. Alexander Zemliak
    System design problem formulation by control theory. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:5-8 [Conf]
  9. Yefim Berkovich, Adrian Ioinovici
    Large-signal stability-oriented design of boost-type regulators in discontinuous conduction mode. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:5-8 [Conf]
  10. A. B. M. Harun-ur Rashid, M. Karim, S. M. Aziz
    Testing complementary pass-transistor logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:5-8 [Conf]
  11. S. L. Liu, S. Mourad, S. Krishnan
    At-speed testing of data communications transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:9-12 [Conf]
  12. Lukai Cai, Daniel Gajski, Mike Olivarez
    Introduction of system level architecture exploration using the SpecC methodology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:9-12 [Conf]
  13. Chung-Chieh Fang
    Sampled-data modeling and analysis of one-cycle control and charge control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:9-12 [Conf]
  14. Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
    Floating-gate CMOS differential analog inverter for ultra low-voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:9-12 [Conf]
  15. N. Nakanishi, Y. Itoh, Y. Fukui, K. Fujii
    Noise reduction system using modified DFT pair. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:9-12 [Conf]
  16. I. Medic, B. Persic
    Simulation model of switching power circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:13-16 [Conf]
  17. S. C. Chan, P. M. Yiu
    Multiplier-less discrete sinusoidal and lapped transforms using sum-of-powers-of-two (sopot) coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:13-16 [Conf]
  18. Ramón González Carvajal, Antonio Jesús Torralba Silgado, Jaime Ramírez-Angulo, Jonathan Noel Tombs, Fernando Muñoz Chavero
    Low voltage class AB output stages for CMOS op-amps using floating capacitors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:13-16 [Conf]
  19. Jong-Yeol Lee, In-Cheol Park
    Global variable localization and transformation for hardware synthesis from high-level programming language description. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:13-16 [Conf]
  20. Shyue-Kung Lu, Chih-Hsien Hsu
    Built-In self-repair for divided word line memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:13-16 [Conf]
  21. Atanas P. Gotchev, N. Nikolaev, Karen O. Egiazarian
    Improving the transform domain ECG denoising performance by applying interbeat and intra-beat decorrelating transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:17-20 [Conf]
  22. O. Woywode, J. Weber, H. Guldner, A. L. Baranovski, W. Schwarz
    Qualitative dynamics of the boost converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:17-20 [Conf]
  23. L. Theriault, D. Auder, Yvon Savaria
    Performance estimators for hardware/software co-design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:17-20 [Conf]
  24. A. S. de la Vega, Antônio Carlos M. de Queiroz, Paulo S. R. Diniz
    Adaptive filter implementation using switched-current technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:17-20 [Conf]
  25. Abdelhakim Khouas, Anne Derieux
    FDP: fault detection probability function for analog circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:17-20 [Conf]
  26. Vladimir I. Prodanov
    Robust high-pass and notch Gm-(grounded) C biquads: how many different topologies are there? [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:21-24 [Conf]
  27. Anthony Vetro, Huifang Sun
    Encoding and transcoding multiple video objects with variable temporal resolution. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:21-24 [Conf]
  28. Z. M. Hussain, Boualem Boashash
    Statistical analysis of the time-delay digital tanlock loop in the presence of Gaussian noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:21-24 [Conf]
  29. Marius Tico, E. Immonen, Pauli Rämö, Pauli Kuosmanen, Jukka Saarinen
    Fingerprint recognition using wavelet features. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:21-24 [Conf]
  30. Y. Inoue, E. Kaji, S. Kasanobu
    A solution-tracing circuit for the fixed-point homotopy method. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:21-24 [Conf]
  31. Tung-Sang Ng, Kun-Wah Yip, Chin-Long Cheng
    An all-lag rotating-reference correlator and its efficient implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:25-28 [Conf]
  32. K. Nandhasri, Jitkasem Ngarmnil
    Designs of analog and digital comparators with FGMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:25-28 [Conf]
  33. Guobin Shen, Bing Zeng, Ya-Qin Zhang, Ming L. Liou
    Transcoder with arbitrarily resizing capability. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:25-28 [Conf]
  34. X. M. Xie, S. C. Chan, T. I. Yuk
    A class of biorthogonal nonuniform cosine-modulated filter banks with lower system delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:25-28 [Conf]
  35. K. Yamamura, T. Kumakura
    Finding all characteristic curves of nonlinear resistive circuits using the dual simplex method. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:25-28 [Conf]
  36. Ki-Cheol Tae, Jin-Gyun Chung, Dae-Ik Kim
    Noise generation system using DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:29-32 [Conf]
  37. Y. Miyanaga, A. Sato, R. HeeBurm
    An image segmentation method with multi-resolution mechanism. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:29-32 [Conf]
  38. Kai-Tat Fung, Yui-Lam Chan, Wan-Chi Siu
    Low-complexity and high quality frame-skipping transcoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:29-32 [Conf]
  39. J. Harrison, Neil Weste
    Energy storage and Gramians of ladder filter realisations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:29-32 [Conf]
  40. M. J. Ogorzalek
    Analysis of a class of constrained nonlinear dynamic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:29-32 [Conf]
  41. R. Begovic, Tapio Saramäki
    A systematic technique for designing prototype filters for perfect reconstruction cosine modulated and modified DFT filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:33-36 [Conf]
  42. H. Nakajima, T. Miyoshi, N. Inaba
    Solvability of network with nonlinear resistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:33-36 [Conf]
  43. Chia-Wen Lin, Jian Zhou, Ming-Ting Sun, Hung Hseng Hsu
    Minimum cost implementation of full VCR functionality in MPEG video streaming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:33-36 [Conf]
  44. Vincent F. Koosh, Rodney M. Goodman
    Dynamic charge restoration of floating gate subthreshold MOS translinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:33-36 [Conf]
  45. Chien-Hsing Wu, Chien-Ming Wu, Ming-Der Shieh, Yin-Tsung Hwang
    Systolic VLSI realization of a novel iterative division algorithm over GF(2m): a high-speed, low-complexity design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:33-36 [Conf]
  46. Yngvar Berg, Snorre Aunet, Øivind Næss, Henning Gundersen, Mats Høvin
    Extreme low-voltage floating-gate CMOS transconductance amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:37-40 [Conf]
  47. W. Zeise, Anton Kummert
    A new image interpolation method for increasing the frame rate in multimedia and virtual reality applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:37-40 [Conf]
  48. Johann Großschädl
    A low-power bit-serial multiplier for finite fields GF(2m). [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:37-40 [Conf]
  49. Min-Chi Kao
    Multiplier-free structures for IIR half-band filter by multiple use of short subfilter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:37-40 [Conf]
  50. Paolo Arena, Luigi Fortuna, Mattia Frasca, C. Marchese
    Multi-template approach to artificial locomotion control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:37-40 [Conf]
  51. Huajian Liu, Xiangwei Kong, Xiangdong Kong, Yu Liu
    Content based color image adaptive watermarking scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:41-44 [Conf]
  52. A. C. McCormick, P. M. Grant, John S. Thompson, Tughrul Arslan, Ahmet T. Erdogan
    A low power MMSE receiver architecture for multi-carrier CDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:41-44 [Conf]
  53. Tamás Roska
    AnaLogic Wave Computers-wave-type algorithms: canonical description, computer classes, and computational complexity. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:41-44 [Conf]
  54. K. T. Christensen
    LC quadrature generation in integrated circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:41-44 [Conf]
  55. Euiseok Kim, Dong-Ik Lee
    A new resource constrained asynchronous scheduling method through transformation of dataflow graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:41-44 [Conf]
  56. Marco Gilli, Mario Biey, Pier Paolo Civalleri, Paolo Checco
    Complex dynamics in cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:45-48 [Conf]
  57. Kong-Pang Pun, José E. Franca, C. Azeredo Leme
    A quadrature sampling scheme with improved image rejection for complex-IF receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:45-48 [Conf]
  58. U. Walther, G. P. Ferrweis
    PN-generators embedded in high performance signal processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:45-48 [Conf]
  59. Wen-Nung Lie, Li-Chun Chang
    Robust and high-quality time-domain audio watermarking subject to psychoacoustic masking. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:45-48 [Conf]
  60. Hen-Ming Lin, Jing-Yang Jou
    On tri-state buffer inference in HDL synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:45-48 [Conf]
  61. T. Shimamura
    Nonuniform amplitude division for ABLMS equalisation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:49-52 [Conf]
  62. Wen-Nung Lie, Guo-Shiang Lin, Ta-Chun Wang
    Digital watermarking for object-based compressed video. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:49-52 [Conf]
  63. Po-Hung Chen, Shanq-Jang Ruan, Kuen-Pin Wu, Dai-Xun Hu, Feipei Lai, Kun-Lin Tsai
    An entropy-based algorithm to reduce area overhead for bipartition-codec architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:49-52 [Conf]
  64. Apinunt Thanachayanont
    A 1.5-V CMOS fully differential inductorless RF bandpass amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:49-52 [Conf]
  65. Csaba Rekeczky, István Szatmári, Péter Földesy
    Computing on silicon with trigger waves: experiments on CNN-UM chips. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:49-52 [Conf]
  66. J. Y. Hassani, Mahmoud Kamarei
    A flexible method of LUT indexing in digital predistortion linearization of RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:53-56 [Conf]
  67. D. Leon, Sina Balkir, Michael W. Hoffman, L. C. Perez
    Robust chaotic PN sequence generation techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:53-56 [Conf]
  68. Richard A. Guinee, C. Lyden
    A novel estimation procedure for the aperture time in asynchronous sinusoidal PWM systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:53-56 [Conf]
  69. Jui-Cheng Yen
    Watermarks embedded in the permuted image. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:53-56 [Conf]
  70. Marc-André Cantin, Yvon Savaria, D. Prodanos, Pierre Lavoie
    An automatic word length determination method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:53-56 [Conf]
  71. Yeong-Kang Lai, Yu-Chuan Shu
    VLSI architecture design and implementation for BLOWFISH block cipher with secure modes of operation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:57-60 [Conf]
  72. Tanes Tanitteerapan, S. Mori
    Fundamental frequency parabolic PWM controller for lossless soft-switching boost power factor correction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:57-60 [Conf]
  73. M. Mir, M. A. Al-Saleh
    A constructive procedure for optimizing the placement of macrocells. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:57-60 [Conf]
  74. Anastasios Tefas, Athanasios Nikolaidis, Nikos Nikolaidis, Vassilios Solachidis, Sofia Tsekeridou, Ioannis Pitas
    Statistical analysis of Markov chaotic sequences for watermarking applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:57-60 [Conf]
  75. J. Vuolevi, J. Manninen, T. Rahkonen
    Cancelling the memory effects in RF power amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:57-60 [Conf]
  76. David Garrett, Mircea R. Stan
    A 2.5 Mb/s, 23 mW SOVA traceback chip for turbo decoding applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:61-64 [Conf]
  77. Bogdan J. Falkowski, Sudha Kannurao
    Calculation of sign Walsh spectra of Boolean functions from disjoint cubes. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:61-64 [Conf]
  78. Esther Rodríguez-Villegas, Adoración Rueda, Alberto Yufera
    A 1.25 V FGMOS filter using translinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:61-64 [Conf]
  79. Holger Boche, Slawomir Stanczak
    Lower bound on mean squared channel estimation error for multiuser receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:61-64 [Conf]
  80. Thomas Olsson, Pontus Åström, Peter Nilsson
    Dual supply-voltage scaling for reconfigurable SoC's. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:61-64 [Conf]
  81. Junaid A. Khan, Sadiq M. Sait, Salman A. Khan
    A fast constructive algorithm for fixed channel assignment problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:65-68 [Conf]
  82. Chung-Hsien Tso, Jiin-Chuan Wu
    An integrated digital PWM DC/DC converter using proportional current feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:65-68 [Conf]
  83. Jorge M. Cañive, Antonio Petraglia
    On the testability of SC filters based on allpass sections. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:65-68 [Conf]
  84. Zhipei Chi, Leilei Song, Keshab K. Parhi
    A study on the performance, complexity tradeoffs of block turbo decoder design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:65-68 [Conf]
  85. Naofal Al-Dhahir, Ayman F. Naguib
    FIR MIMO decision feedback equalization for space-time block-coded transmission over multipath-fading channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:65-68 [Conf]
  86. M. Olivieri
    A genetic approach to the design space exploration of superscalar microprocessor architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:69-72 [Conf]
  87. Joarez B. Monteiro, Antonio Petraglia, C. Azeredo Leme
    A digitally programmable IIR switched-capacitor filter for CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:69-72 [Conf]
  88. Håkan Bengtson, Christer Svensson
    3V CMOS 0.35 µ transimpedance receiver for optical applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:69-71 [Conf]
  89. J. Thalheim, Norbert Felber, Wolfgang Fichtner
    A new approach for controlling series-connected IGBT modules. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:69-72 [Conf]
  90. J. Shimizu
    Adaptive blind signal separation using a risk-sensitive criterion. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:69-72 [Conf]
  91. Shyh-Jye Jou, Shu-Hua Kuo, Jui-Ta Chiu, Chu King, Chien-Hsiung Lee, Tim Liu
    A serial link transceiver for USB2 high-speed mode. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:72-75 [Conf]
  92. J. Panoff, S. Nagaraj, S. Gollamudi, Yih-Fang Huang, Josef A. Nossek
    A minimax approach to open-loop downlink beamforming. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:73-76 [Conf]
  93. Mohammad H. Tehranipour, Zainalabedin Navabi, Seid Mehdi Fakhraie
    An efficient BIST method for testing of embedded SRAMs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:73-76 [Conf]
  94. L. C. C. Marques, Carlos Galup-Montoro, Sidnei Noceti Filho, Márcio C. Schneider
    Switched-MOSFET technique for programmable filters operating at low-voltage supply. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:73-76 [Conf]
  95. Xin Li, Bo Hu, Xieting Ling, Xuan Zeng
    A wavelet balance approach for steady-state analysis of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:73-76 [Conf]
  96. Inseop Lee, W. Kenneth Jenkins
    Pipelined implementation of the adaptive canceller-equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:76-80 [Conf]
  97. L. C. C. Marques, Carlos Galup-Montoro, Sidnei Noceti Filho, Márcio C. Schneider
    A switched-MOSFET filter for application in hearing aid devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:77-80 [Conf]
  98. Chien-Cheng Tseng, Su-Ling Lee
    Design of digital differentiator based on maximum signal to noise ratio criterion. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:77-80 [Conf]
  99. Fong-Ming Shyu, Sao-Jie Chen
    A distributed and object-oriented framework for VLSI physical design automation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:77-80 [Conf]
  100. Irwin W. Sandberg, G. J. J. Van Zyl
    Evaluation of the response of nonlinear systems to asymptotically almost periodic inputs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:77-80 [Conf]
  101. Chua-Chin Wang, Po-Ming Lee, Rong-Chin Lee, Chenn-Jung Huang
    A 1.25 GHz 32-bit tree-structured carry lookahead adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:80-83 [Conf]
  102. Kangmin Lee, Chi Weon Yoon, Ramchan Woo, Jeong-Hun Kook, Ja-Il Koo, Tae-Sung Jung, Hoi-Jun Yoo
    A comparative performance analysis of a DDR-SDRAM, a D-RDRAM, and a DDR-FCRAM using a POPeye simulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:81-84 [Conf]
  103. Jaewook Lee, Hsiao-Dong Chiang
    A trajectory-based methodology for systematically computing multiple optimal solutions of general nonlinear programming problems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:81-84 [Conf]
  104. J.-J. Fuchs
    A class of approximate FIR low-pass filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:81-84 [Conf]
  105. Saeid Nooshabadi
    Modelling of effects of temperature profile in the MOS transistor characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:81-84 [Conf]
  106. Henrik Eriksson, Per Larsson-Edefors, Atila Alvandpour
    A 2.8 ns 30 uW/MHz area-efficient 32-b Manchester carry-bypass adder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:84-87 [Conf]
  107. A. G. Deczky
    Unispherical windows. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:85-88 [Conf]
  108. Jirayuth Mahattanakul, C. Bunyakate
    Harmonic injection method: a novel method for harmonic distortion analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:85-88 [Conf]
  109. Kisun Kim, Taekyoon Ahn, Sang-Yeol Han, Chang-Seung Kim, Ki-Hyun Kim
    Low-power multiplexer decomposition by suppressing propagation of signal transitions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:85-88 [Conf]
  110. Mao-Feng Lan, Randall L. Geiger
    Modeling of random channel parameter variations in MOS transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:85-88 [Conf]
  111. Chung-Hsun Huang, Jinn-Shyan Wang, Yan-Chao Huang
    A high-speed CMOS incrementer/decrementer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:88-91 [Conf]
  112. Kazutoshi Kobayashi, Hidetoshi Onodera
    ST: PERL package for simulation and test environment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:89-92 [Conf]
  113. P. Mundkur, Rui J. P. de Figueiredo
    Scaled simplicial approximation for the inversion of Gaussian RBF expansions. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:89-92 [Conf]
  114. Yukio Mori, Naoyuki Aikawa
    The transfer function of low delay maximally flat lowpass FIR digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:89-92 [Conf]
  115. Mao-Feng Lan, Randall L. Geiger
    MOSGRAD-a tool for simulating the effects of systematic and random channel parameter variations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:89-92 [Conf]
  116. Andreas Wassatsch, Dirk Timmermann
    Scalable counter architecture for a pre-loadable 1 GHz@0.6 um/5V pre-scaler in TSPC. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:92-95 [Conf]
  117. Md. A. Razzak, Bing Zeng
    Multiple description image transmission for diversity systems using block-based DC separation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:93-96 [Conf]
  118. Saed Samadi, Akinori Nishihara
    Response of maximally flat lowpass filters to polynomial signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:93-96 [Conf]
  119. M. Hanggi, Leon O. Chua
    Compact bistable CNNs based on resonant tunneling diodes. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:93-96 [Conf]
  120. D. B. Carvalho, Sidnei Noceti Filho, Rui Seara
    Q-GA: a modified genetic algorithm for the design of phase equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:93-96 [Conf]
  121. Juan A. Montiel-Nelson, V. de Armas, Roberto Sarmiento, Antonio Núñez, Saeid Nooshabadi
    A compact layout technique to minimize high frequency switching effects in high speed circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:96-99 [Conf]
  122. V. Mladenov, Hans Hegt, Arthur H. M. van Roermund
    Terminal dynamics approach to cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:97-100 [Conf]
  123. Aigang Feng, Xiaojun Wu, Qinye Yin
    Fast algorithm of adaptive chirplet-based real signal decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:97-100 [Conf]
  124. Mark Schlarmann, Randall L. Geiger
    Prototype implementation of a WWW based analog circuit design tool. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:97-100 [Conf]
  125. Feng Wu, Shipeng Li, Ya-Qin Zhang
    Progressive fine granular scalable (PFGS) video using advance-predicted bitplane coding (APBIC). [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:97-100 [Conf]
  126. H. Zarei, Omid Shoaei, Seid Mehdi Fakhraie
    A low-power fully integrated Gaussian-MSK modulator based on the sigma-delta fractional-N frequency synthesis. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:100-103 [Conf]
  127. Wenjie Wang, Aigang Feng, Qinye Yin
    Optimal linear space-time multiuser detector for asynchronous DS-CDMA system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:101-104 [Conf]
  128. Hyongsuk Kim, Hongrak Son, Tamás Roska, Leon O. Chua
    Dependant distance potential source algorithm for optimal path finding with the analogic CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:101-104 [Conf]
  129. Supavadee Aramvith, Chia-Wen Lin, Sumit Roy, Ming-Ting Sun
    Wireless video transport using conditional retransmission and low-delay interleaving. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:101-104 [Conf]
  130. Jader A. De Lima, A. S. Cordeiro
    An accurate low-voltage analog memory-cell with built-in multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:101-104 [Conf]
  131. Xiaohong Sun, K. R. Laker
    A new design for cascaded sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:104-107 [Conf]
  132. M. Namba, S. Takatori, H. Kawabata, Z. Zhang
    The variable neighborhood CNN. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:105-108 [Conf]
  133. Keng Hoong Wee, Toshiyuki Nozawa, T. Yonezawa, Y. Yamashita, Tadashi Shibata, Tadahiro Ohmi
    High-precision analog EEPROM with real-time write monitoring. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:105-108 [Conf]
  134. H. C. So
    Adaptive multipath equalization time delay estimation with bias-removal. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:105-108 [Conf]
  135. Nikolaos V. Boulgouris, Athanasios Leontaris, Nikolaos Thomos, Michael G. Strintzis
    Robust layered coding of video for transmission over noisy channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:105-108 [Conf]
  136. B. Voss, Manfred Glesner
    A low power sinusoidal clock. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:108-111 [Conf]
  137. Z. M. Hussain, Boualem Boashash
    Multicomponent IF estimation: a statistical comparison in the quadratic class of time-frequency distributions. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:109-112 [Conf]
  138. Wenwu Zhu, Qian Zhang, Ya-Qin Zhang
    Network-adaptive rate control with unequal loss protection for scalable video over Internet. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:109-112 [Conf]
  139. Xiaoqiang Shou, M. M. Green
    A family of CMOS latches with 3 stable operating points. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:109-112 [Conf]
  140. Pedro Julián, Radu Dogaru, Leon O. Chua
    A piecewise-linear simplicial coupling cell for CNN gray-level image processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:109-112 [Conf]
  141. Massimo Alioto, Giuseppe Di Cataldo, Gaetano Palumbo
    CML ring oscillators: oscillation frequency. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:112-115 [Conf]
  142. Sheng-hong Li, Hong-Wen Zhu
    Harmonic retrieval in mixed non-Gaussian and gaussian ARMA noises using higher-order statistics. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:113-116 [Conf]
  143. S. Sriram, R. Tandon, Pallab Dasgupta, P. P. Chakrabarti
    Symbolic verification of Boolean constraints over partially specified functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:113-116 [Conf]
  144. Chien-Cheng Yu, Wei-Ping Wang, Bin-Da Liu
    A new level converter for low-power applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:113-116 [Conf]
  145. Ngamroo Ngamroo
    Application of static synchronous series compensator (SSSC) to stabilization of frequency oscillations in an interconnected power system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:113-116 [Conf]
  146. Yijun Zhou, Jiren Yuan
    An 8-Bit, 100-MHz low glitch interpolation DAC. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:116-119 [Conf]
  147. D. Chaniotis, M. A. Pai, Ian A. Hiskens
    Sensitivity analysis of differential-algebraic systems using the GMRES method-application to power systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:117-120 [Conf]
  148. Wei Xing Zheng
    A computationally efficient scheme for estimating linear noisy input-output systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:117-120 [Conf]
  149. Wei Wang, Malgorzata Chrzanowska-Jeske
    A global approach to the variable ordering problem in PSBDDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:117-120 [Conf]
  150. J. Pihl, K. T. Christensen, Erik Bruun
    Direct downconversion with switching CMOS mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:117-120 [Conf]
  151. F. Xavier Moncunill-Geniz, O. Mas-Casals, Pere Palà-Schönwälder
    A comparative analysis of direct-sequence spread-spectrum super-regenerative architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:120-123 [Conf]
  152. S. Peungsungwal, B. Pungsiri, Kosin Chamnongthai, M. Okuda
    Autonomous robot for a power transmission line inspection. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:121-124 [Conf]
  153. S. Reda, Ayman M. Wahba, Ashraf M. Salem, Dominique Borrione, M. Ghonaimy
    On the use of don't cares during symbolic reachability analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:121-124 [Conf]
  154. Chung-Yu Wu, Chung-Yun Chou
    The design of a CMOS IF bandpass amplifier with low sensitivity to process and temperature variations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:121-124 [Conf]
  155. Wei Xing Zheng
    Unbiased parameter identification for noisy autoregressive signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:121-124 [Conf]
  156. Kari Stadius, P. Jarvio, Petteri Paatsila, Kari Halonen
    Image-reject receivers with image-selection functionality. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:124-127 [Conf]
  157. Saffet Ayasun, Chika Nwankpa, H. G. Kwatny
    Parameter space depiction of stability limits in the presence of singularities. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:125-128 [Conf]
  158. K. Kantapanit, P. Inrawongs, W. Wiriyasuttiwong, R. Kantapanit
    Dental caries lesions detection using deformable templates. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:125-128 [Conf]
  159. Jatindra Kumar Deka, S. Chaki, Pallab Dasgupta, P. P. Chakrabarti
    Abstractions for model checking of event timings. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:125-128 [Conf]
  160. M. Dawkins, A. Payne, N. Cowley
    Single chip tuner design for digital terrestrial television. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:125-128 [Conf]
  161. Sridhar Rajagopal, Joseph R. Cavallaro
    A bit-streaming, pipelined multiuser detector for wireless communication receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:128-131 [Conf]
  162. L. Ivanov, R. Nunna
    Modeling and verification of cache coherence protocols. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:129-132 [Conf]
  163. C. K. T. Chan, Christofer Toumazou
    Design of a class E power amplifier with non-linear transistor output capacitance and finite DC-feed inductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:129-132 [Conf]
  164. Issarachai Ngamroo
    Design of robust H-infty via normalized coprime factorization approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:129-132 [Conf]
  165. Are Hjørungnes, Tapio Saramäki
    Minimum mean square error quantizers with uncorrelated input and quantization noise. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:129-132 [Conf]
  166. F. S. Tsai, Chen-Yi Lee
    A novel single-bit input all digital synchronizer and demodulator baseband processor for fast frequency hopping system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:132-135 [Conf]
  167. Y. Kawasaki, Toshimichi Saito, Hiroyuki Torikai
    Quantized chaotic dynamics and communications systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:133-136 [Conf]
  168. Mohamed Lamine Tounsi, Mustapha Chérif-Eddine Yagoub, B. Haraoubia
    Hybrid analysis of shielding effect in planar microwave circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:133-136 [Conf]
  169. C. H. Yeh, C. J. Kuo
    Content-based retrieval from nonstationary image database. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:133-136 [Conf]
  170. Sumohana S. Channappayya, Glen P. Abousleman, Lina J. Karam
    Joint source-channel coding of images using punctured convolutional codes and trellis-coded quantization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:133-136 [Conf]
  171. S. Makido, Takaya Yamazato, Hiraku Okada, Masaaki Katayama, Akira Ogawa
    A design of source matched MAP receiver for image transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:136-139 [Conf]
  172. Qian Zhang, Wenwu Zhu, Zu Ji, Ya-Qin Zhang
    A power-optimized joint source channel coding for scalable video streaming over wireless channel. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:137-140 [Conf]
  173. F. Agnelli, Gianluca Mazzini, Riccardo Rovatti, Gianluca Setti
    A first experimental verification of optimal MAI reduction in chaos-based DS-CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:137-140 [Conf]
  174. Francesc Serra-Graells
    All-MOS subthreshold log filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:137-140 [Conf]
  175. Wenmiao Lu, Yap-Peng Tan
    A color histogram based people tracking system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:137-140 [Conf]
  176. Yiannis Moisiadis, I. Bouras, Angela Arapoyanni
    A CMOS differential logic for low-power and high-speed applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:140-143 [Conf]
  177. Andrea Cavallaro, Touradj Ebrahimi
    Change detection based on color edges. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:141-144 [Conf]
  178. Emmanuel M. Drakakis, A. J. Payne, Christofer Toumazou, A. E. J. Ng, John I. Sewell
    High-order lowpass and bandpass elliptic log-domain ladder filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:141-144 [Conf]
  179. Géza Kolumbán, Michael Peter Kennedy
    Recent results for chaotic modulation schemes. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:141-144 [Conf]
  180. Quji Guo, Qian Zhang, Wenwu Zhu, Ya-Qin Zhang
    A sender-adaptive and receiver-driven layered multicast scheme for video over Internet. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:141-144 [Conf]
  181. Frank Grassert, Dirk Timmermann
    Dynamic single phase logic with self-timed stages for power reduction in pipeline circuit designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:144-147 [Conf]
  182. G. D. Duerden, Gordon W. Roberts, M. Jamal Deen
    The development of bipolar log domain filters in a standard CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:145-148 [Conf]
  183. M. Hasler
    Ergodic chaos shift keying. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:145-148 [Conf]
  184. Baofeng Guo, Kin-Man Lam, Wan-Chi Siu, Shuyuan Yang
    Human face recognition using a spatially weighted Hausdorff distance. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:145-148 [Conf]
  185. J. McEachen, A. Cay
    Masking compressed video connection utilization in ATM networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:145-148 [Conf]
  186. Hongchin Lin, Yi-Fan Chen, Hsien-Chih She
    A low-power 3-phase half rail pass-gate differential logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:148-151 [Conf]
  187. Chi-Chung Chen, Kung Yao
    Design of spread spectrum sequences using chaotic dynamical systems with Lebesgue spectrum. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:149-152 [Conf]
  188. Mohammed E. Al-Mualla, Cedric Nishan Canagarajah, David R. Bull
    Multiple-reference temporal error concealment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:149-152 [Conf]
  189. A. E. J. Ng, John I. Sewell, Emmanuel M. Drakakis, A. J. Payne, Chris Toumazou
    A unified matrix method for systematic synthesis of log-domain ladder filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:149-152 [Conf]
  190. Guo-Shiang Lin, Wen-Nung Lie
    A study on detecting image hiding by feature analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:149-152 [Conf]
  191. K. Y. Cheung
    CRRDL: a novel charge recovery-recycling differential logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:152-153 [Conf]
  192. P. Zavarsky, Noriyoshi Kambayashi, Somchart Chokchaitam, Masahiro Iwahashi, M. Kamiya
    A signal reconstruction method based on an unwrapping of signals in transform domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:153-156 [Conf]
  193. Gian Mario Maggio, Luca Reggiani
    Applications of symbolic dynamics to UWB impulse radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:153-156 [Conf]
  194. T. Yamaoki, S. Taoka, T. Watanabe
    Extracting a planar spanning subgraph of a terminal-vertex graph by solving the independent set problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:153-156 [Conf]
  195. Julius Georgiou, Christofer Toumazou
    An operating point elimination technique for weak-inversion log-domain filters with multiple operating points. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:153-155 [Conf]
  196. Seong-Ook Jung, Seung-Moon Yoo, Ki-Wook Kim, Sung-Mo Kang
    Skew-tolerant high-speed (STHS) domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:154-157 [Conf]
  197. A. Lopez-Martinez, R. Antonio-Chavez, J. Silva-Martinez
    A 150 MHz continuous-time seventh order 0.05° equiripple linear phase filter with automatic tuning system. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:156-159 [Conf]
  198. Luiz W. P. Biscainho, Paulo S. R. Diniz, P. A. A. Esquef
    ARMA processes in sub-bands with application to audio restoration. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:157-160 [Conf]
  199. Zhangsu Bing, Liu Ze-Min
    Neural network training using ant algorithm in ATM traffic control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:157-160 [Conf]
  200. Muthukumar Venkatesan, Robert J. Bignall, Henry Selvaraj
    A variable partition approach for disjoint decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:157-162 [Conf]
  201. Seong-Ook Jung, Ki-Wook Kim, Sung-Mo Kang
    Noise constrained power optimization for dual VT domino logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:158-161 [Conf]
  202. Drazen Jurisic, George S. Moschytz, Neven Mijat
    Low-sensitivity SAB band-pass active-RC filter using impedance tapering. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:160-163 [Conf]
  203. Hisham Othman, Tyseer Aboulnasr
    A simplified second-order HMM with application to face recognition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:161-164 [Conf]
  204. A. Niruntasukrat, W. Benjapolakul
    A novel scheme for policing mechanism in ATM networks: feedback fuzzy leaky bucket. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:161-164 [Conf]
  205. I. Thoidis, Dimitrios Soudris, J. M. Fernandez, Adonios Thanailakis
    The circuit design of multiple-valued logic voltage-mode adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:162-165 [Conf]
  206. N. Chandrachoodan, S. S. Bhattacharyya, K. J. Ray Liu
    Adaptive negative cycle detection in dynamic graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:163-166 [Conf]
  207. U. Yodprasit, K. Sirivathanant
    A compact low-power vertical filter for very-high-frequency applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:164-167 [Conf]
  208. W. Benjapolakul, A. Niruntasukrat, P. Nanagara
    Backward predictive congestion control notification in ATM networks using neural network prediction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:165-168 [Conf]
  209. T. Phiasai, S. Arunrungrusmi, Kosin Chamnongthai
    Face recognition system with PCA and moment invariant method. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:165-168 [Conf]
  210. Henrik Eriksson, Per Larsson-Edefors, William P. Marnane
    A regular parallel multiplier which utilizes multiple carry-propagate adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:166-169 [Conf]
  211. Shun-Wen Cheng, Kuo-Hsing Cheng
    ENISLE: an intuitive heuristic nearly optimal solution for mincut and ratio mincut partitioning. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:167-170 [Conf]
  212. A. Aga, Gordon W. Roberts
    A CMOS digitally programmable current steering semidigital FIR reconstruction filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:168-171 [Conf]
  213. M. Hasegawa, Gang Wu, M. Mizuni
    Applications of nonlinear prediction methods to the Internet traffic. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:169-172 [Conf]
  214. George A. Triantafyllidis, Michael G. Strintzis
    A least squares algorithm for efficient context-based adaptive arithmetic coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:169-172 [Conf]
  215. Pasi Liljeberg, Juha Plosila, Jouni Isoaho
    Asynchronous interface for locally clocked modules in ULSI systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:170-173 [Conf]
  216. Naofumi Homma, Takafumi Aoki, Tatsuo Higuchi
    Evolutionary graph generation system with transmigration capability for arithmetic circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:171-174 [Conf]
  217. U. Yodprasil, K. Sirivathanani
    VHF current-mode filter based on intrinsic biquad of the regulated cascode topology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:172-175 [Conf]
  218. C. Dualibe, Paul G. A. Jespers, Michel Verleysen
    Embedded fuzzy control for automatic channel equalization after digital transmissions. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:173-176 [Conf]
  219. Y. C. Lim, Y. J. Yu, H. Q. Zheng, S. W. Foo
    FPGA implementation of digital filters synthesized using the frequency-response masking technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:173-176 [Conf]
  220. Nazmy Abaskharoun, Mohamed Hafed, Gordon W. Roberts
    Strategies for on-chip sub-nanosecond signal capture and timing measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:174-177 [Conf]
  221. Hong Li, Bee June Tye, Ee Ping Ong, Weisi Lin, Chi Chung Ko
    Multiple motion object segmentation based on homogenous region merging. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:175-178 [Conf]
  222. P. Amini, Omid Shoaei
    A low-power gigabit Ethernet analog equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:176-179 [Conf]
  223. Tapio Saramäki, Håkan Johansson
    Optimization of FIR filters using the frequency-response masking approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:177-180 [Conf]
  224. F. L. Degertekin, N. A. Hall
    Micromachined microphone with optical interferometric readout. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:177-180 [Conf]
  225. Wen-Tsong Shiue
    Leakage power estimation and minimization in VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:178-181 [Conf]
  226. K. F. Chan, Y. T. Wong, C. W. Kok
    Multiresolution mesh representation using vertex cluster contraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:179-182 [Conf]
  227. Amorn Jiraseree-amornkun, B. Chipipop, Wanlop Surakampontorn
    Novel translinear-based multi-output FTFN. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:180-183 [Conf]
  228. Ralph Etienne-Cummings, Matthew A. Clapp
    Architecture for source localization with a linear ultrasonic array. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:181-184 [Conf]
  229. Oscar Gustafsson, Håkan Johansson, Lars Wanhammar
    Narrow-band and wide-band single filter frequency masking FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:181-184 [Conf]
  230. Huo-Hsing Cheng, Ven-Chieh Hsieh
    A new logic synthesis and optimization procedure. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:182-185 [Conf]
  231. Alexis M. Tourapis, Oscar C. Au, Ming L. Liou
    New results on zonal based motion estimation algorithms-advanced predictive diamond zonal search. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:183-186 [Conf]
  232. Liping Deng, John G. Harris
    The design and analysis of an analog ratio spectrum circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:184-187 [Conf]
  233. Juha Yli-Kaakinen, Tapio Saramäki
    A systematic algorithm for the design of multiplierless FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:185-188 [Conf]
  234. André van Schaik, Eric Fragnière
    Pseudo-voltage domain implementation of a 2-dimensional silicon cochlea. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:185-188 [Conf]
  235. Artur Wróblewski, O. Schumecher, Christian V. Schimpfle, Josef A. Nossek
    Minimizing gate capacitances with transistor sizing. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:186-189 [Conf]
  236. Wujian Zhang, Runde Zhou, T. Kondo
    Low-power motion-estimation architecture based on a novel early-jump-out technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:187-190 [Conf]
  237. Dalibor Biolek, Viera Biolkova
    Optimization of frequency filters via vertex graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:188-191 [Conf]
  238. A. Groth, H. G. Gockler
    Efficient minimum group delay block processing approach to fractional sample rate conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:189-192 [Conf]
  239. Andreas G. Andreou, David H. Goldberg, Eugenio Culurciello, Milutin Stanacevic, Gert Cauwenberghs, Laurence Riddle
    Heterogeneous integration of biomimetic acoustic microsystems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:189-192 [Conf]
  240. Ming-Jun Hsiao, Jing-Reng Huang, Shao-Shen Yang, Tsin-Yuan Chang
    A low-cost CMOS time interval measurement core. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:190-193 [Conf]
  241. Christoph Scholl, Marc Herbstritt, Bernd Becker
    Exploiting don't cares to minimize *BMDs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:191-194 [Conf]
  242. A. Tong, Paul J. Hurst
    A mixed-signal tuning approach for continuous-time LPFs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:192-195 [Conf]
  243. Hao-Chieh Chang, Zhong-Lan Yang, Chung-Jr Lian, Liang-Gee Chen
    Hardware-efficient architecture design of tree-depth scanning and multiple quantization scheme for MPEG-4 still texture coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:193-196 [Conf]
  244. Gert Cauwenberghs, Milutin Stanacevic, G. Zweig
    Blind broadband source localization and separation in miniature sensor arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:193-196 [Conf]
  245. T. Santti, Jouni Isoaho
    Modified SRCMOS cell for high-throughput wave-pipelined arithmetic units. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:194-197 [Conf]
  246. Sudhakar Bobba, Ibrahim N. Hajj
    Input vector generation for maximum intrinsic decoupling capacitance of VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:195-198 [Conf]
  247. G. Pamisano, Salvatore Pennisi
    New CMOS tunable transconductor for filtering applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:196-199 [Conf]
  248. Christoforos N. Hadjicostis, George C. Verghese
    Power system monitoring based on relay and circuit breaker information. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:197-200 [Conf]
  249. Hyeon-Cheol Mo, Jong-Sun Kim, Lee-Sup Kim
    A high-speed pattern decoder in MPEG-4 padding block hardware accelerator. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:197-200 [Conf]
  250. Felix Lustenberger, Hans-Andrea Loeliger
    On mismatch errors in analog-VLSI error correcting decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:198-201 [Conf]
  251. Janusz A. Starzyk, D. Liu
    Multiple fault diagnosis of analog circuits by locating ambiguity groups of test equation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:199-202 [Conf]
  252. Roman Kaszynski
    The parametric filter of signal constant component. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:200-203 [Conf]
  253. C. Singh, Ian A. Hiskens
    Direct assessment of transient singularity in differential-algebraic systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:201-204 [Conf]
  254. Petros Daras, Ioannis Kompatsiaris, Theodoros Raptis, Michael G. Strintzis
    MPEG-4 authoring tool for the composition of 3D audiovisual scenes. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:201-204 [Conf]
  255. Tong Zhang, Zhongfeng Wang, Keshab K. Parhi
    On finite precision implementation of low density parity check codes decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:202-205 [Conf]
  256. Hiroshi Tsutsui, K. Hiwada, Tomonori Izumi, Takao Onoye, Yukihiro Nakamura
    A design of LUT-array-based PLD and a synthesis approach based on sum of generalized complex terms expression. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:203-206 [Conf]
  257. Seng-Pan U., Rui Paulo Martins, José E. Franca
    High-frequency low-power multirate SC realizations for NTSC/PAL digital video filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:204-207 [Conf]
  258. Keun-Sup Lee, Hyen-O Oh, Young-Cheol Park, Dae Hee Youn
    High quality MPEG-audio layer III algorithm for a 16-bit DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:205-208 [Conf]
  259. K. E. Holbert, G. T. Heydt
    Prospects for dynamic transmission circuit ratings. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:205-208 [Conf]
  260. Chien-Ming Wu, Ming-Der Shieh, Chien-Hsing Wu, Ming-Hwa Sheu
    VLSI architecture of extended in-place path metric update for Viterbi decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:206-209 [Conf]
  261. Mei-Juan Chen, Chih-Wei Pan, Jeng-Wei Chen, Ro-Min Weng
    Multiple region-of-interest image coding with embedded watermark. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:207-210 [Conf]
  262. Xiaoqiang Shou, M. Green
    A programmable VHF CMOS read-channel continuous-time filter with on-chip tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:208-211 [Conf]
  263. Chung-Chieh Fang, E. H. Abed
    Harmonic balance analysis and control of period doubling bifurcation in buck converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:209-212 [Conf]
  264. Olli Lehtoranta, Timo Hämäläinen, Jukka Saarinen
    Parallel implementation of H.263 encoder for CIF-sized images on quad DSP system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:209-212 [Conf]
  265. M. Traber
    A novel ACS-feedback scheme for generic, sequential Viterbi-decoder macros. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:210-213 [Conf]
  266. Simon Tredwell, Adrian N. Evans
    Block grouping algorithm for motion description encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:211-214 [Conf]
  267. Jader A. De Lima, Antonio Petraglia
    On designing OTA-C graphic-equalizers with MOSFET-triode transconductors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:212-215 [Conf]
  268. H. Yu, H. Leung
    A comparative study of different chaos based spread spectrum communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:213-216 [Conf]
  269. Xiaojun Wu, Aigang Feng, Qinye Yin
    Universal discrete model and linear algebra representation for variant OFDM-CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:213-216 [Conf]
  270. M. Traber
    A low power survivor memory unit for sequential Viterbi-Decoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:214-217 [Conf]
  271. Richard P. Kleihorst, Anteneh A. Abbo, Andre van der Avoird, M. Op de Beeck, Leo Sevat, Paul Wielage, R. van Veen, H. van Herten
    Xetal: a low-power high-performance smart camera processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:215-218 [Conf]
  272. Bjørnar Hernes, Øystein Moldsvor, T. Saether
    A -80 dB HD3 opamp in 3.3 V CMOS technology using tail current compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:216-219 [Conf]
  273. Gianluca Mazzini, Riccardo Rovatti, Gianluca Setti
    Improved performance estimation and optimization for chaos-based asynchronous DS-CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:217-220 [Conf]
  274. Jun Inagaki, Miki Haseyama, Hideo Kitajima
    A new genetic algorithm for routing the shortest route via several designated points. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:217-220 [Conf]
  275. Youngjoon Kim, Lee-Sup Kim
    A low power carry select adder with reduced area. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:218-221 [Conf]
  276. Jian Feng, Tie-Yan Liu, Kwok-Tung Lo, Xu-Dong Zhang
    Adaptive motion tracking for fast block motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:219-222 [Conf]
  277. Hoi Lee, Philip K. T. Mok
    A CMOS current-mirror amplifier with compact slew rate enhancement circuit for large capacitive load applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:220-223 [Conf]
  278. Eric Debes
    A new Petri net based model of data transfers in the PC workstation memory hierarchy for MPEG encoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:221-224 [Conf]
  279. Sergio Callegari, M. Dondini, Gianluca Setti
    Adaptive median thresholding for the generation of high-data-rate random-like unpredictable binary sequences with chaos. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:221-224 [Conf]
  280. V. A. Bartlett, Andrew G. Dempster
    Using carry-save adders in low-power multiplier blocks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:222-225 [Conf]
  281. Bedabrata Pain, Suresh Seshadri, Monico Ortiz, Chris Wrigley, Guang Yang
    CMOS imager with charge-leakage compensated frame difference and sum output. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:223-226 [Conf]
  282. V. Rentala, S. Rout, E. Lee, R. J. Weber
    A constant GM rail-to-rail opamp with a novel input stage for BiCMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:224-227 [Conf]
  283. Vinay Varadan, Henry Leung
    Design of piece-wise maps for spread spectrum communication using genetic programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:225-228 [Conf]
  284. Kees G. W. Goossens
    A protocol and memory manager for on-chip communication. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:225-228 [Conf]
  285. Ayman A. Fayed, Magdy A. Bayoumi
    A low power 10-transistor full adder cell for embedded architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:226-229 [Conf]
  286. Chung-Neng Wang, Tihao Chiang, Chi-Min Liu, Hung-Ju Lee
    Improved MPEG-4 visual texture coding using double transform coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:227-230 [Conf]
  287. Jie Yan, Randall L. Geiger
    Fast-settling CMOS operational amplifiers with negative conductance voltage gain enhancement. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:228-231 [Conf]
  288. Jie Chen
    SONET transcoder design for ATM over SONET or directly over fiber. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:229-232 [Conf]
  289. H. Fujisaki
    On optimum 3-phase spreading sequences of simple Markov chains. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:229-232 [Conf]
  290. Gang Xu, Jiren Yuan
    An embedded low power FIR filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:230-233 [Conf]
  291. Hua Cai, Bing Zeng
    A new SPIHT algorithm based on variable sorting thresholds. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:231-234 [Conf]
  292. M. M. Amourah, Randall L. Geiger
    Gain and bandwidth boosting techniques for high-speed operational amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:232-235 [Conf]
  293. Vincent F. Koosh, Rodney M. Goodman
    VLSI neural network with digital weights and analog multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:233-236 [Conf]
  294. Yuwen He, Bo Feng, Shiqiang Yang, Yichuo Zhong
    Fast global motion estimation for global motion compensation coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:233-236 [Conf]
  295. S. Klauke, J. Gotze
    Low power enhancements for parallel algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:234-237 [Conf]
  296. K. H. Leung, Bing Zeng
    Wavelet-based digital watermarking with halftoning technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:235-238 [Conf]
  297. Yuanying Deng, E. K. F. Lee
    Design of a 1 V 250 MHz current-mode filter in conventional CMOS process. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:236-239 [Conf]
  298. Mahmoud Al-Nsour, Hoda S. Abdel-Aty-Zohdy
    MOS fully analog reinforcement neural network chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:237-240 [Conf]
  299. A. Ahmed, S. K. Nandy, Paul Sathya
    Content adaptive motion estimation for mobile video encoders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:237-240 [Conf]
  300. Kasin Vichienchom, Mark Clements, Wentai Liu
    A multi-gigabit CMOS data recovery circuit using an analog parallel sampling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:238-241 [Conf]
  301. Jiwu Huang, Yun Q. Shi
    Embedding gray level images. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:239-242 [Conf]
  302. Tertulien Ndjountche, Rolf Unbehauen
    A low-power and high-speed equalizer for magnetic storage read channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:240-243 [Conf]
  303. David H. Goldberg, Gert Cauwenberghs, Andreas G. Andreou
    Analog VLSI spiking neural network with address domain probabilistic synapses. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:241-244 [Conf]
  304. Hsien-Hsi Hsieh, Yong-Kang Lai
    A novel fast motion estimation algorithm using fixed subsampling pattern and multiple local winners search. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:241-244 [Conf]
  305. R. K. Jain, R. Frenzel, M. Terschluse, P. K. Pandey, S. H. Low, B. Sukumaran, L. M. Lam
    System-on-chip design of a four-port ADSL-lite Data DSP. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:242-245 [Conf]
  306. Ming Sun Fu, Oscar C. Au
    Improved halftone image data hiding with intensity selection. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:243-246 [Conf]
  307. J. K. Pyykonen
    A low distortion wideband active-RC filter for a multicarrier base station transmitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:244-247 [Conf]
  308. Qiang Luo, John G. Harris
    A novel neural oscillator and its implementation in analog VLSI. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:245-248 [Conf]
  309. Mei-Yun Hsu, Hao-Chieh Chang, Yi-Chu Wang, Liang-Gee Chen
    Scalable module-based architecture for MPEG-4 BMA motion estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:245-248 [Conf]
  310. Yuyu Chang, Jack Wills, John Choma Jr.
    On-chip automatic direct tuning circuitry based on the synchronous rectification scheme for CMOS gigahertz band front-end filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:246-249 [Conf]
  311. Tobias Schüle, Albrecht P. Stroele
    Scheduling tests for low power built-in self-test. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:247-250 [Conf]
  312. Phanumas Khumsat, Apisak Worapishet
    fT-integration based continuous-time filters for very high frequencies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:248-251 [Conf]
  313. Warnakulasuriya Anil Chandana Fernando, Cedric Nishan Canagarajah, David R. Bull
    Scene adaptive video encoding for MPEG and H263+ video. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:249-252 [Conf]
  314. Amine Bermak, D. Martinez
    A compact multi-chip-module implementation of a multi-precision neural network classifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:249-252 [Conf]
  315. Chi-Li Yu, An-Yeu Wu
    An improved time-recursive lattice structure for low-latency IFFT architecture in DMT transmitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:250-253 [Conf]
  316. Paul M. Rosinger, Bashir M. Al-Hashimi, Nicola Nicolici
    Power constrained test scheduling using power profile manipulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:251-254 [Conf]
  317. G. Palaskas, Yannis P. Tsividis
    A "divide and conquer" technique for the design of wide dynamic range continuous time filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:252-255 [Conf]
  318. Saverio Mascolo, Giuseppe Grassi
    Controlling chaotic systems with disturbance: a new approach based on backstepping design and nonlinear damping. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:253-256 [Conf]
  319. W. Chiracharit, P. N. N. Ayudhya, K. Chamnongthai
    Detection of calcifications in digitized mammograms using wavelet packet analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:253-256 [Conf]
  320. S. Huss, J. Bennett
    An efficient model for twisted-pair cables with discontinuities and stubs for discrete time simulations. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:254-257 [Conf]
  321. V. Muresan, Xiaojun Wang, Mircea Vladutiu
    A combined tree growing technique for block-test scheduling under power constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:255-258 [Conf]
  322. Yonghui Tang, Randall L. Geiger
    A 2.5 Gbit/s CMOS PLL for data/clock recovery without frequency divider. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:256-259 [Conf]
  323. R. Barsanti, M. Tummala
    Parameter estimation for target tracking with uncertain sensor positions. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:257-260 [Conf]
  324. K. Konishi, H. Kokame, K. Hirata
    Spatial instability in one-way open coupled double-scroll circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:257-260 [Conf]
  325. J. McEachen, Ow Kong Chung, Lim Chin Thong
    A system level description and model of Signaling System No 7. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:258-261 [Conf]
  326. Chun-Yao Wang, Shing-Wu Tung, Jing-Yang Jou
    An AVPG for SOC design verification with port order fault model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:259-262 [Conf]
  327. Jinghui Lu, B. Grung, S. Anderson, S. Rokhsaz
    Discrete z-domain analysis of high order phase locked loops. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:260-263 [Conf]
  328. Chai Wah Wu
    Simple three oscillator universal probes for determining synchronization stability in coupled arrays of oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:261-264 [Conf]
  329. S. A. Aldosari, Saleh A. Alshebeili, Abdulhameed M. Al-Sanie
    Combined linear-decision feedback sequence estimation: an improved system design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:261-264 [Conf]
  330. Wael M. Badawy, Magdy A. Bayoumi
    A mesh based motion tracking architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:262-265 [Conf]
  331. Donald Shaw, Dhamin Al-Khalili, Come Rozon
    Deriving accurate ASIC cell fault models for VITAL compliant VHDL simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:263-266 [Conf]
  332. Abdelouahab Djemouai, Mohamad Sawan
    Fast-locking low-jitter integrated CMOS phase-locked loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:264-267 [Conf]
  333. Saman S. Abeysekera, Kabi Prakash Padhi, Javed Absar, Sapna George
    Investigation of different frequency estimation techniques using the phase vocoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:265-268 [Conf]
  334. A. Hasegawa, T. Endo
    Multimode oscillations in a four fully-interconnected Van Der Pol oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:265-268 [Conf]
  335. Jin-Ku Kang, Dong-Hee Kim
    A CMOS clock and data recovery with two-XOR phase-frequency detector circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:266-269 [Conf]
  336. Sunho Chang, Lee-Sup Kim
    Design trade-off in merged DRAM logic for video signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:267-270 [Conf]
  337. K. Suzuki, T. Tsubone, T. Saito
    Analysis of partial constant return map from controlled manifold piecewise linear chaotic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:269-272 [Conf]
  338. Fan Xu, Alan N. Willson Jr.
    Local stability analysis and hardware realization of an eigenvector tracking algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:269-272 [Conf]
  339. B. Siddik Yarman, Ahmet Aksen
    A reflectance-based computer aided modelling tool for high speed/high frequency communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:270-273 [Conf]
  340. Chung-Bin Wu, Bin-Da Liu, Jar-Ferr Yang
    Adaptive postprocessors with DCT-based block classifications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:271-274 [Conf]
  341. Jin-Jer Jong, Chen-Yi Lee
    A novel structure for portable digitally controlled oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:272-275 [Conf]
  342. W. Ohno, T. Endo
    Property of the double heteroclinic tangency crisis in a forced PLL equation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:273-276 [Conf]
  343. Sazzadur Chowdhury, Majid Ahmadi, Graham A. Jullien, William C. Miller
    A MEMS implementation of an acoustical sensor array. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:273-276 [Conf]
  344. Ronald P. Luijten, T. Engbersen, Cyriel Minkenberg
    Shared memory switching + virtual output queuing: A robust and scalable switch. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:274-277 [Conf]
  345. Shao-Yi Chien, Yu-Wen Huang, Shyh-Yih Ma, Liang-Gee Chen
    A hybrid morphology processing units architecture for real-time video segmentation systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:275-278 [Conf]
  346. Hassan Aboushady, Marie-Minerve Louërat
    Low-power design of low-voltage current-mode integrators for continuous-time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:276-279 [Conf]
  347. Shahrokh Ahmadi, Mona E. Zaghloul
    Signal conditioning for Fabry-Perot sensor. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:277-280 [Conf]
  348. Luigi Fortuna, Mattia Frasca, Alessandro Rizzo
    Frequency hysteresis phenomena in the frequency switched Chua's circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:277-280 [Conf]
  349. Mostafa I. Abd-El-Barr, C. Sundarram, A. S. Almulhem
    VLSI considerations in the design of k-ary n-cube interconnection networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:278-281 [Conf]
  350. M. Kacarska, S. Loskovska, D. Andonov
    The advantages of multiprocessor systems for ACEIT and ICEIT inverse problem solution. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:279-282 [Conf]
  351. Peter Kiss, Un-Ku Moon, Jesper Steensgaard, John T. Stonick, Gabor C. Temes
    Multibit Sigma-Delta ADC with mixed-mode DAC error correction. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:280-283 [Conf]
  352. A. Hodge, Robert W. Newcomb, A. Hefner
    Use of the oscillation based built-in self-test method for smart sensor devices. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:281-284 [Conf]
  353. Takuji Kousaka, M. Matsumoto, Tetsushi Ueta, Hiroshi Kawakami, M. Abe
    Bifurcation analysis in hybrid nonlinear dynamical systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:281-284 [Conf]
  354. Di He, Chen He, Ling-ge Jiang, Hong-Wen Zhu, Guang-Rui Hu
    Phase tracking of CDMA spreading sequences using dynamic chaotic synchronization. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:282-285 [Conf]
  355. K. A. Jung, Y. S. Lee, H. S. Yang, W. S. Yang, J. H. Kim, S. H. Lee, B. H. Kang
    An integrated H.263 video CODEC with protocol processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:283-286 [Conf]
  356. Zhenghong Wang, Xieting Ling
    Noise-reducing loop in multi-bit Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:284-287 [Conf]
  357. M. T. Moskowitz, Louiza Sellami, Robert W. Newcomb, V. Rodellar
    Current mode realization of ear-type multisensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:285-288 [Conf]
  358. H. Kitajima, H. Kawakami
    Bifurcation in coupled BVP neurons with external impulsive forces. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:285-288 [Conf]
  359. Chin-Liang Wang, Ming-Hung Li, Kuo-Ming Wu, Kwei-Liang Hwang
    Adaptive interference suppression with power control for CDMA systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:286-289 [Conf]
  360. Wen-Nung Lie, Bo-Er Wei
    Intermediate view synthesis from binocular images for stereoscopic applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:287-290 [Conf]
  361. Omid Oliaei
    Clock jitter effect in continuous-time oversampling converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:288-291 [Conf]
  362. P. Gómez, A. Alvarez, R. Martínez, V. Nieto, V. Rodellar
    Frequency-domain steering for negative beamformers in speech enhancement and directional source separation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:289-292 [Conf]
  363. M. Shepard, R. C. Williamson
    Very low voltage power conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:289-292 [Conf]
  364. Kyungtae Han, Iksu Eo, Kyungsu Kim, HanJin Cho
    Numerical word-length optimization for CDMA demodulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:290-293 [Conf]
  365. Andrew G. Dempster, Cecilia Di Ruberto
    Using granulometries in processing images of malarial blood. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:291-294 [Conf]
  366. Omid Oliaei
    Continuous-time sigma-delta modulator with an arbitrary feedback waveform. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:292-295 [Conf]
  367. Wei Chen, Wing-Hung Ki, Philip K. T. Mok, Mansun Chan
    Switched-capacitor power converters with integrated low dropout regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:293-296 [Conf]
  368. Wei-Yong Yan, Kok Lay Teo
    Optimum discrete coefficient realization of FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:293-296 [Conf]
  369. Jing Lei, Tung-Sang Ng
    New AFC algorithm for a fully-digital MDPSK DS/CDMA receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:294-297 [Conf]
  370. D. R. Clewer, L. J. Luo, Cedric Nishan Canagarajah, David R. Bull, M. H. Barton
    Efficient multiview image compression using quadtree disparity estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:295-298 [Conf]
  371. Andrea Gerosa, Arianna Novo, A. Mengalli, Andrea Neviani
    A micro-power low noise log-domain amplifier for the sensing chain of a cardiac pacemaker. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:296-299 [Conf]
  372. J. Zhang, A. K. M. Wu, Henry S. H. Chung
    On the use of pseudo-coevolutionary genetic algorithms with adaptive migration for design of power electronics regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:297-300 [Conf]
  373. W.-S. Lu
    Design of FIR filters with discrete coefficients: a semidefinite programming relaxation approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:297-300 [Conf]
  374. X. M. Wang, Wu-Sheng Lu, Andreas Antoniou
    A near-optimal multiuser detector for CDMA channels using semidefinite programming relaxation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:298-301 [Conf]
  375. Lizhong Peng, Minghui Wang
    An embedded wavelet-based quadtree interframe coding algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:299-302 [Conf]
  376. E. Ibaragi, S. Nishioka, A. Hyogo, K. Sekine
    A CMOS OTA free from second order effects with a high input resistance Gm control terminal. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:300-303 [Conf]
  377. Chia-Yu Yao
    A study of SPT-term distribution of CSD numbers and its application for designing fixed-point linear phase FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:301-304 [Conf]
  378. Dongsheng Ma, Wing-Hung Ki, Philip K. T. Mok, Chi-Ying Tsui
    Single-inductor multiple-output switching converters with bipolar outputs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:301-304 [Conf]
  379. Y. Bajot, H. Mehrez
    Customizable DSP architecture for ASIP core design. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:302-305 [Conf]
  380. Anshul Sehgal, Ashish Jagmohan, Narendra Ahuja
    Wireless video conferencing using multiple description coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:303-306 [Conf]
  381. Wen-Chi Wu, Chih-Chien Huang, Nai-Heng Tseng
    CMOS transimpedance amplifier for DVD applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:304-307 [Conf]
  382. Alberto Nannarelli, Marco Re, Gian-Carlo Cardarilli
    Tradeoffs between residue number system and traditional FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:305-308 [Conf]
  383. Janusz Zarebski
    A new electrothermal dynamic macromodel of the power Darlington transistor for SPICE. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:305-308 [Conf]
  384. T. S. Jarvinen, J. H. Takala, David Akopian, J. P. P. Saarinen
    Register-based multi-port perfect shuffle networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:306-309 [Conf]
  385. Leonid B. Goldgeisser, Ernst Christen, Milan Vlach, Joachim Langenwalter
    Open ended dynamic ramping simulation of multi-discipline systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:307-310 [Conf]
  386. Rosario Mita, Gaetano Palumbo, Salvatore Pennisi
    Reversed nested Miller compensation with current follower. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:308-311 [Conf]
  387. M. Kaneko, Y. Maekawa
    Extended dimensional threshold filtering-a bridge between FIR filter and median type filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:309-312 [Conf]
  388. Thomas Schimming
    Chaos based modulations from an information theory perspective. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:309-312 [Conf]
  389. Hiroshi Nakada, Hideyuki Ito, Ryusuke Konishi, Akira Nagoya, Kiyoshi Oguri, Tsunemichi Shiozawa, Norbert Imlig
    Self-reorganising systems on VLSI circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:310-313 [Conf]
  390. Paolo Crippa, Massimo Conti, Claudio Turchetti
    A statistical methodology for the design of high-performance current steering DAC's. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:311-314 [Conf]
  391. Giovanni Palmisano, Salvatore Pennisi
    Low-voltage continuous-time CMOS current amplifier with dynamic biasing. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:312-315 [Conf]
  392. T. Ozawa
    An integral image and text processing system for automatic generation of 3D sign-language animations. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:313-316 [Conf]
  393. Zbigniew Galias, Gian Mario Maggio
    Quadrature chaos shift keying. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:313-316 [Conf]
  394. S. Mortezapour, E. K. F. Lee
    A reconfigurable pipelined data converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:314-317 [Conf]
  395. G. Reissig
    On methods for ordering sparse matrices in circuit simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:315-318 [Conf]
  396. T. Hollman, Saska Lindfors, Teemu Salo, M. Lansirinne, Kari Halonen
    A 2.7 V CMOS dual-mode baseband filter for GSM and WCDMA. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:316-319 [Conf]
  397. Yuan-Chung Lee, Chein-Wei Jen
    Arbitrarily scalable edge-preserving interpolation for 3-D graphics and video resizing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:317-320 [Conf]
  398. Francis Chi-Moon Lau, M. M. Yip, C. K. Tse, S. F. Hau
    A multiple access technique for differential chaos shift keying. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:317-320 [Conf]
  399. A. E. Bashagha
    Novel radix-2k division algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:318-321 [Conf]
  400. N. Chandra, Gordon W. Roberts
    Top-down analog design methodology using Matlab and Simulink. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:319-322 [Conf]
  401. Seng-Pan U., Rui Paulo Martins, José E. Franca
    A high-speed frequency up-translated SC bandpass filter with auto-zeroing for DDFS systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:320-323 [Conf]
  402. Naoki Masuda, Kazuyuki Aihara
    Cryptosystems based on space-discretization of chaotic maps. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:321-324 [Conf]
  403. Wei Jyh Heng, King Ngi Ngan
    Shot classification for hard transition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:321-324 [Conf]
  404. J. G. Lim, C. C. Lim
    A parallel architecture for estimating 4th-order cumulants. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:322-325 [Conf]
  405. A. Fakhfakh, N. Milet-Lewis, Yann Deval, H. Levi
    Study and behavioural simulation of phase noise and jitter in oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:323-326 [Conf]
  406. Gianfranco Avitabile, B. Chellini, G. Fedi, Antonio Luchetta, Stefano Manetti
    MMIC active floating gyrator design and accurate modelling. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:324-327 [Conf]
  407. Ana C. Andrés del Valle, Jörn Ostermann
    3D talking head customization by adapting a generic model to one uncalibrated picture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:325-328 [Conf]
  408. P. Chiang, William J. Dally, E. Lee
    Monolithic chaotic communications system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:325-328 [Conf]
  409. Yew-San Lee, Cheng-Mou Yu, Chen-Yi Lee
    Error resilient hybrid variable length codec with tough error synchronization for wireless image transmission. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:326-329 [Conf]
  410. Masaya Suzuki, H. Miyashita, Atsushi Kamo, Takayuki Watanabe, Hideki Asai
    High-speed interconnect simulation using MIMO type of adaptive least square method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:327-330 [Conf]
  411. Hengsheng Liu, Aydin I. Karsilayan
    A high frequency bandpass continuous-time filter with automatic frequency and Q-factor tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:328-331 [Conf]
  412. Ronald Tetzlaff, Ronald Kunz
    Spatio-temporal distribution of brain electrical activity patterns in epilepsy: inputs for cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:329-332 [Conf]
  413. M. Hasan, Farrokh Marvasti
    A cascaded MAP-based linear prediction (CMAP-LP) error concealment technique for consecutive block losses. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:329-332 [Conf]
  414. Wei-Hsin Chang, Yew-San Lee, Wen-Shiaw Peng, Chen-Yi Lee
    A line-based, memory efficient and programmable architecture for 2D DWT using lifting scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:330-333 [Conf]
  415. D. Strle
    Capacitor-area and power-consumption optimization of high-order Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:331-334 [Conf]
  416. Tsung-Sum Lee, Jing-Lea Huang
    A low-voltage BiCMOS transconductor with improved linearity for VHF transconductance-C filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:332-335 [Conf]
  417. F. Werblin, Botond Roska, Dávid Bálya, Csaba Rekeczky, Tamás Roska
    Implementing a retinal visual language in CNN: a neuromorphic study. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:333-336 [Conf]
  418. A. Charoenpanitkit, N. Sivamok, Lunchakorn Wuttisittikulkij
    An analysis of a new access control technique for channel request in wireless communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:333-336 [Conf]
  419. Christos Drosos, Chrissavgi Dre, Spyros Blionas, Dimitrios Soudris
    On the implementation of a baseband processor for a portable dual mode DECT/GSM terminal. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:334-337 [Conf]
  420. Zongmou Yin
    Symbolic network analysis with the valid trees and the valid tree-pairs. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:335-338 [Conf]
  421. P. K. Singh, Franco Maloberti
    Design considerations for band-pass sigma delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:336-339 [Conf]
  422. Ch. V. Verikoukis, J. J. Oimos
    Optimization of the DQRUMA MAC protocol for multimedia traffic in an OFDM based W-ATM system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:337-340 [Conf]
  423. Bertram Emil Shi
    CNN models of current mode neuromorphic networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:337-340 [Conf]
  424. Li-Hsun Chen, Oscal T.-C. Chen
    A low-complexity and high-speed Booth-algorithm FIR architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:338-341 [Conf]
  425. K. Tsuji, A. Ohta
    An extended Petri net III and its applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:339-342 [Conf]
  426. José Manuel de la Rosa, Maria Belen Pérez-Verdú, F. Medeiro, Rocio del Río, Ángel Rodríguez-Vázquez
    Effect of non-linear settling error on the harmonic distortion of fully-differential switched-current bandpass Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:340-343 [Conf]
  427. H. L. Lai, L. K. Chen, Y. B. Lee
    VBR video delivery using monotonic-decreasing rate scheduling. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:341-344 [Conf]
  428. M. Brucoli, D. Cafagna, L. Carnimeo
    On the performance of CNNs for associative memories in robot vision systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:341-344 [Conf]
  429. A.-O. Dahmane, Daniel Massicotte, Leszek Szczecinski
    A VLSI architecture of a piecewise RBF decision feedback channel equalizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:342-345 [Conf]
  430. Massimo De Santo, Nicola Femia, Mario Molinara, Giovanni Spagnuolo
    Multi agent systems for circuit tolerance and sensitivity analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:343-346 [Conf]
  431. A. Yahias, P. Benabes, R. Kielbasa
    Bandpass Delta-Sigma modulators synthesis with high loop delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:344-347 [Conf]
  432. Paolo Arena, Luigi Fortuna, Luigi Occhipinti
    DNA chip image processing via cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:345-348 [Conf]
  433. Fei Xue, Velibor Markovski, Ljiljana Trajkovic
    Packet loss in video transfers over IP networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:345-348 [Conf]
  434. Shyue-Win Wei
    Cellular-array power-sum circuits over programmable finite field GF(2'''). [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:346-349 [Conf]
  435. Yi-He Jiang, Jianbang Lai, Ting-Chi Wang
    Module placement with pre-placed modules using the B*-tree representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:347-350 [Conf]
  436. M. Keskin, Un-Ku Moon, Gabor C. Temes
    Low-voltage low-sensitivity switched-capacitor bandpass Sigma-Delta modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:348-351 [Conf]
  437. J. R. Epps, W. H. Holmes
    A new very low bit rate wideband speech coder with a sinusoidal highband model. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:349-352 [Conf]
  438. M. Salerno, F. Sargeni, V. Bonaiuto
    A new CNN IC for stereo visual system. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:349-352 [Conf]
  439. Marco Re, Alberto Nannarelli, Gian-Carlo Cardarilli, Roberto Lojacono
    FPGA realization of RNS to binary signed conversion architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:350-353 [Conf]
  440. Ingmar Neumann, Wolfgang Kunz
    Tight coupling of timing-driven placement and retiming. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:351-354 [Conf]
  441. Teemu Salo, Saska Lindfors, Kari Halonen
    A low-voltage single-Opamp 4th-order band-pass Sigma-Delta-modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:352-355 [Conf]
  442. S. J. Nam, B. H. Kim, C. D. Im, J. B. Kim, S. J. Lee, S. S. Jeong, J. K. Kim, S. J. Park
    A low power MPEG I/II layer 3 audio decoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:353-356 [Conf]
  443. M. A. Hasan, A. A. Hasan
    Matrix inverse-free algorithms for the general eigenvalue problem. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:353-356 [Conf]
  444. Yin-Tsung Hwang, Jih-Cheng Han, Jing-Yi Liu
    Design and implementation of channel equalizers for block transmission systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:354-357 [Conf]
  445. Habib Youssef, Sadiq M. Sait, H. Ali
    Adaptive bias simulated evolution algorithm for placement. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:355-358 [Conf]
  446. Kofi A. A. Makinwa, Johan H. Huijsing
    A wind-sensor with integrated interface electronics. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:356-359 [Conf]
  447. Francisco del Águìla López, Pere Palà-Schönwälder, Jordi Bonet-Dalmau, M. Rosa Giralt-Mas
    A discrete-time technique for the steady state analysis of nonlinear switched circuits with inconsistent initial conditions. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:357-360 [Conf]
  448. Jongseo Sohn, Suhong Ryu, Wonyong Sung
    A codebook shaping method for perceptual quality improvement of CELP coders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:357-360 [Conf]
  449. Ching-Chi Chang, Chien-Chih Lin, Muh-Tian Shiue, Chorng-Kuang Wang
    A wide pull-in range fast acquisition hardware-sharing two-fold carrier recovery loop. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:358-361 [Conf]
  450. Hendrik Hartje, Ingmar Neumann, Dominik Stoffel, Wolfgang Kunz
    Cycle time optimization by timing driven placement with simultaneous netlist transformations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:359-362 [Conf]
  451. D. Moraes, Francis Anghinolfi, Philippe Deval, P. Jarron, W. Riegler, A. Rivetti, B. Schmidt
    CARIOCA-0.25 Sigma-Delta CMOS fast binary front-end for sensor interface using a novel current-mode feedback technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:360-363 [Conf]
  452. Jaewook Lee, Hsiao-Dong Chiang
    Computation of multiple type-one equilibrium points on the stability boundary using generalized fixed-point homotopy methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:361-364 [Conf]
  453. Selma Özaydin, Buyurman Baykal
    Matrix quantization based speech coder at 1200 bps. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:361-364 [Conf]
  454. W. Younis, Naofal Al-Dhahir
    FIR prefilter design for MLSE equalization of space-time-coded transmission over multipath fading channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:362-365 [Conf]
  455. Philippe Maurine, Mustapha Rezzoug, Daniel Auvergne
    Output transition time modeling of CMOS structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:363-366 [Conf]
  456. N. Haralabidis, D. Loukas
    A versatile CMOS low-noise analog front-end stage for solid state detector interfaces. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:364-367 [Conf]
  457. Hea-Kyoung Jung, Yu-Jin Kim, Jae-Ho Chung
    The implementation of PFCMS using cepstrum information. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:365-368 [Conf]
  458. Jaewook Lee, Hsiao-Dong Chiang
    Quotient gradient methods for solving constraint satisfaction problems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:365-368 [Conf]
  459. R. Lopez-Valcarce, S. DasGupta
    Second order statistics based blind channel equalization with correlated sources. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:366-369 [Conf]
  460. N. Chandrachoodan, S. S. Bhattacharyya, K. J. Ray Liu
    The hierarchical timing pair model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:367-370 [Conf]
  461. M. A. P. Pertijs, A. Bakker, Johan H. Huijsing
    A high-accuracy temperature sensor with second-order curvature correction and digital bus interface. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:368-371 [Conf]
  462. Yuval Bistritz
    Scattering and immittance type tabular stability tests for 2-D discrete-time systems and their simplification by telepolation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:369-372 [Conf]
  463. Stefano Pastore, Amedeo Premoli
    DC tolerance analysis of electronic circuits by linear programming techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:369-372 [Conf]
  464. Ediz Çetin, Izzet Kale, Richard C. S. Morling
    Adaptive compensation of analog front-end I/Q mismatches in digital receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:370-373 [Conf]
  465. Ki-Wook Kim, Seong-Ook Jung, Sung-Mo Kang
    Coupling-aware minimum delay optimization for domino logic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:371-374 [Conf]
  466. P. K. Chan, H. L. Zhang
    A switched-capacitor interface circuit for integrated sensor applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:372-375 [Conf]
  467. Zhiping Lin, Jiang Qian Ying, Li Xu
    Further results on primitive factorizations for nD polynomial matrices. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:373-376 [Conf]
  468. Y. Hosokawa, Yoshifumi Nishio, Akio Ushida
    A design method of chaotic circuits using an oscillator and a resonator. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:373-376 [Conf]
  469. Xiaopeng Li, Mohammed Ismail
    A single-chip CMOS front-end receiver architecture for multi-standard wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:374-377 [Conf]
  470. Nadine Azémard, M. Aline, Daniel Auvergne
    Delay bound determination for timing closure satisfaction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:375-378 [Conf]
  471. T. Tille, Jörg Sauerbrey, Doris Schmitt-Landsiedel
    A low-voltage MOSFET-only Sigma-Delta modulator for speech band applications using depletion-mode MOS-capacitors in combined series and parallel compensation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:376-379 [Conf]
  472. S. S. Lawson, J. G. Guzman
    On the modelling of the 2D wave equation using multidimensional wave digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:377-380 [Conf]
  473. Xiaoqiang Shou, Leonid B. Goldgeisser, M. M. Green
    A methodology for constructing two-transistor multistable circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:377-380 [Conf]
  474. Tang Jing Jung, King Sau Cheung, J. Lau
    A 2.4 GHz four port mixer for direct conversion used in telemetering. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:378-381 [Conf]
  475. M. Hashimoto, H. Onodeva
    Increase in delay uncertainty by performance optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:379-382 [Conf]
  476. Saska Lindfors
    Behavior of a 1-bit 2nd-order Sigma-Delta-modulator under wideband excitation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:380-383 [Conf]
  477. S. Nagata, Y. Horio
    Influences of anti-aliasing filter on estimation of the largest Lyapunov exponent. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:381-384 [Conf]
  478. K. Mori
    Stably-freeness and multidimensional systems with structural stability. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:381-384 [Conf]
  479. Kalle Kivekäs, A. Parssinen, Jarkko Jussila, Jussi Ryynänen, Kari Halonen
    Design of low-voltage active mixer for direct conversion receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:382-385 [Conf]
  480. D. Zhou, Wei Li, W. Cai, N. Guo
    An efficient balanced truncation realization algorithm for interconnect model order reduction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:383-386 [Conf]
  481. Antonio Jesús Torralba Silgado, Francisco Colodro Ruiz
    Multirate-cascade sigma-delta (MC-SD) modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:384-387 [Conf]
  482. M. Hu, David Z. Gevorkian, Olli Vainio
    One- and two-dimensional order statistic filter design with FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:385-388 [Conf]
  483. Chin-Hwa Kuo, Tay-Shen Wang
    A real-time segmentation scheme for continuous color images. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:385-388 [Conf]
  484. Zhaofeng Zhang, L. Tsui, Zhiheng Chen, J. Lau
    A CMOS self-mixing-free front-end for direct conversion applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:386-389 [Conf]
  485. W. Li, D. Zhou, H. Kim, X. Zeng
    Automatic clock tree design with IPs in the system. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:387-390 [Conf]
  486. Lee-An Ho, Shr-Lung Chen, Chien-Hung Kuo, Shen-Iuan Liu
    CMOS oversampling Sigma-Delta magnetic to digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:388-391 [Conf]
  487. Rudi Prosen, Miro Milanovic, Drago Dolinar
    Unity IDF correction for AC to DC converter based on modulation strategy. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:389-392 [Conf]
  488. Cheng-Hung Chuang, Wen-Nung Lie
    Automatic snake contours for the segmentation of multiple objects. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:389-392 [Conf]
  489. Hung Yan Cheung, King Sau Cheung, J. Lau
    A low power monolithic AGC with automatic DC offset cancellation for direct conversion hybrid CDMA transceiver used in telemetering. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:390-393 [Conf]
  490. X. Zeng, D. Zhou
    Design of GHz VLSI clock distribution circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:391-394 [Conf]
  491. M. A. Aldajani, A. H. Sayed
    SNR performance of an adaptive sigma delta modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:392-395 [Conf]
  492. D. Kawamoto, H. Sekiya, Hirotaka Koizumi, Iwao Sasase
    Design of a generalized phase-controlled class E inverter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:393-396 [Conf]
  493. S. Saha, Ranga Vemuri
    Use of adaptive integer-to-integer wavelet transforms in lossless image coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:393-396 [Conf]
  494. Harri Lampinen, Olli Vainio
    Dynamically biased current sensor for current-sensing completion detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:394-397 [Conf]
  495. Subhashis Majumder, Susmita Sur-Kolay, Bhargab B. Bhattacharya, Subhas C. Nandy
    Area(number)-balanced hierarchy of staircase channels with minimum crossing nets. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:395-398 [Conf]
  496. Jorge Guilherme, Pedro M. Figueiredo, P. Azevedo, G. Minderico, A. Leal, João C. Vital, José E. Franca
    A pipeline 15-b 10-Msample/s analog-to-digital converter for ADSL applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:396-399 [Conf]
  497. Kamon Jirasereeamornkul, Y. Roungraungpalangkul, Kosin Chamnongthai
    A single stage single switch power factor correction converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:397-400 [Conf]
  498. Qi Wang, Feng Wu, Shipeng Li, Zixiang Xiong, Ya-Qin Zhang, Yuzhuo Zhong
    A new rate allocation scheme for progressive fine granular scalable coding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:397-400 [Conf]
  499. Yavuz Kiliç, Mark Zwolinski
    Process variation independent built-in current sensor for analogue built-in self-test. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:398-401 [Conf]
  500. Charles J. Alpert, Gopal Gandham, Jiang Hu, José Luis Neves, Stephen T. Quay, Sachin S. Sapatnekar
    Steiner tree optimization for buffers. Blockages and bays. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:399-402 [Conf]
  501. Chunlei Shi, J. Wilson, Mohammed Ismail
    Design techniques for improving intrinsic accuracy of resistor string DACs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:400-403 [Conf]
  502. M. Raad, Ian S. Burnett
    Audio coding using sorted sinusoidal parameters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:401-404 [Conf]
  503. P. A. Mawby, P. M. Igic, M. S. Towers
    New physics-based compact electro-thermal model of power diode dedicated to circuit simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:401-404 [Conf]
  504. Gaetano Palumbo, D. Pappalardo, M. Gaibotti
    Modeling and minimization of power consumption in charge pump circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:402-405 [Conf]
  505. D. Kim, T. Ambler
    Robust transition density estimation by considering input/output transition behavior. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:403-406 [Conf]
  506. Johan Piper, Jiren Yuan
    Realization of a floating-point A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:404-407 [Conf]
  507. Maciej Ogorzalek
    Approximation and compression of arbitrary time-series based on nonlinear dynamics. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:405-408 [Conf]
  508. Chien-Cheng Tseng, Su-Ling Lee
    Elimination of power line interference and noise in electrocardiogram using constrained eigenfilter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:405-408 [Conf]
  509. Sheng-Yeh Lai, Jinn-Shyan Wang
    A high-efficiency CMOS charge pump circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:406-409 [Conf]
  510. Jiwei Chen, Bingxue Shi
    Pulsed activation: Saving power for mixed-signal circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:407-410 [Conf]
  511. Sameer R. Sonkusale, Jan Van der Spiegel, K. Nagaraj
    Background digital error correction technique for pipelined analog-digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:408-411 [Conf]
  512. Qingwen Zhang, Wasfy B. Mikhael
    Application of the two dimensional frequency domain least squares algorithm to airborne surveillance radar detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:409-412 [Conf]
  513. R. Lopez-Valcarce, S. DasGupta
    Blind equalization of nonlinear digital satellite links with PSK modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:409-412 [Conf]
  514. Joshua L. Garrett, Mircea R. Stan
    Active threshold compensation circuit for improved performance in cooled CMOS systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:410-413 [Conf]
  515. Imed Ben Dhaou, Hannu Tenhunen, Vijay Sundararajan, Keshab K. Parhi
    Energy efficient signaling in DSM CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:411-414 [Conf]
  516. B. R. Greenley, Un-Ku Moon, R. Veith
    A 1.8 V CMOS DAC cell with ultra high gain op-amp in 0.0143 mm2. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:412-415 [Conf]
  517. Irwin W. Sandberg
    The recovery of distorted bandlimited almost-periodic signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:413-416 [Conf]
  518. H. Gaunholt
    A subharmonic detrending or data-smoothing approach for longitudinal road profile measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:413-416 [Conf]
  519. Rongtian Zhang, Kaushik Roy, Cheng-Kok Koh, David B. Janes
    Power trends and performance characterization of 3-dimensional integration. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:414-417 [Conf]
  520. Wen-Tsong Shiue
    Energy efficient memory assignment. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:415-418 [Conf]
  521. Gerry Quilligan, D. P. Burton
    A high-speed subranging system with background equalization of the sampling instants. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:416-419 [Conf]
  522. K. Ola Andersson, N. U. Andersson, J. Jacob Wikner
    Spectral shaping of DAC nonlinearity errors through modulation of expected errors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:417-420 [Conf]
  523. Der-Zheng Liu, Che-Ho Wei
    DAPSK-OFDM transmissions for high date-rate digital mobile radio. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:417-420 [Conf]
  524. Q. K. Zhu, M. Zhang
    Low-voltage swing clock distribution schemes. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:418-421 [Conf]
  525. Maurits Ortmanns, Friedel Gerfers, Yiannos Manoli
    On the synthesis of cascaded continuous-time Sigma-Delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:419-422 [Conf]
  526. N. Kurosawa, H. Kobayashi, K. Kobayashi
    Channel linearity mismatch effects in time-interleaved ADC systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:420-423 [Conf]
  527. S. Barbabella, Francesco Piazza, Aurelio Uncini
    Complex domain flexible non-linear function for blind signal separation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:421-424 [Conf]
  528. Wei-Ping Zhu, M. Omair Ahmad, M. N. S. Swamy
    A fully digital timing recovery scheme using two samples per symbol. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:421-424 [Conf]
  529. Dimitrios Velenis, Eby G. Friedman, Marios C. Papaefthymiou
    A clock tree topology extraction algorithm for improving the tolerance of clock distribution networks to delay uncertainty. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:422-425 [Conf]
  530. Y. Dong, Ajoy Opal
    An overview on computer-aided analysis techniques for sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:423-426 [Conf]
  531. S. Hamedi-Hagh, C. Andre T. Salama
    A 10 bit, 50 M sample/s, low power pipelined A/D converter for cable modem applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:424-427 [Conf]
  532. N. E. Mastorakis, M. N. S. Swamy
    A method for computing the stability margin of two-dimensional continuous systems based on Hermite matrices. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:425-428 [Conf]
  533. Eelco Rouw, Jaap Hoekstra, Arthur H. M. van Roermund
    Spike correlation based learning for unsupervised neural lattice structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:425-428 [Conf]
  534. Mohamed Nekili, Yvon Savaria, Guy Bois
    Minimizing process-induced skew using delay tuning. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:426-429 [Conf]
  535. H. Shibata, N. Fujii
    Analog circuit synthesis by superimposing of sub-circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:427-430 [Conf]
  536. A. R. Bugeja, Sung-Ung Kwak
    Design of a 14 b 100 MS/s switched-capacitor pipelined ADC in RFSiGe BiCMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:428-431 [Conf]
  537. M. French, Eric Rogers, H. Wibowo, David H. Owens
    A 2D systems approach to iterative learning control based on nonlinear adaptive control techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:429-432 [Conf]
  538. Hyongsuk Kim, Youngsu Park, Tamás Roska, Leon O. Chua
    Optimal path finding with space variant metric weights via multilayer CNN-UM. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:429-432 [Conf]
  539. Luca Fanucci, R. Roncella, Roberto Saletti
    Non-linearity reduction technique for delay-locked delay-lines. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:430-433 [Conf]
  540. Alex Doboli, Ranga Vemuri
    Hierarchical performance optimization for synthesis of linear analog systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:431-434 [Conf]
  541. C. Pala, L. Thylen, M. Mokhtari, U. Westergren
    A high-speed electro-optical analog-to-digital converter principle. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:432-435 [Conf]
  542. Qun Gao, P. Forster, K. R. Mobus, George S. Moschytz
    Fingerprint recognition using CNNs: fingerprint preprocessing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:433-436 [Conf]
  543. Nirmal K. Bose, Surapong Lertrattanapanich, J. Koo
    Advances in superresolution using L-curve. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:433-436 [Conf]
  544. Martin Makundi, Vesa Välimäki, Timo I. Laakso
    Closed-form design of tunable fractional-delay allpass filter structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:434-437 [Conf]
  545. Nuno F. Paulino, João Goes, Adolfo Steiger-Garção
    Design methodology for optimization of analog building blocks using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:435-438 [Conf]
  546. Eduardo J. Peralías, Adoración Rueda, José L. Huertas
    Structural testing of pipelined analog to digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:436-439 [Conf]
  547. Tian-Bo Deng
    Design of variable 2-D digital filters with perfect linear-phase using matrix-array decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:437-440 [Conf]
  548. F. Lobato-Lopez, José Silva-Martínez, Edgar Sánchez-Sinencio
    Linear cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:437-440 [Conf]
  549. Shou-Sheu Lin, Wen-Rong Wu
    A low complexity adaptive interpolated FIR echo canceller. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:438-441 [Conf]
  550. K. R. Whight
    A novel time domain method for computing phase noise in resonant oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:439-442 [Conf]
  551. J. Mayer, Rui Seara, Sidnei Noceti Filho, R. dos Santos
    Analytical approach for compensation of the D/A conversion effect. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:440-443 [Conf]
  552. Hyungju Park
    2-D non-separable paraunitary matrices and Grobner bases. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:441-444 [Conf]
  553. S. Kongrattanaprasert, S. Arunrungrusmi, B. Pungsiri, Kosin Chamnongthai, M. Okuda
    Nondestructive maturity determination of durian by force vibration. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:441-444 [Conf]
  554. L. C. Chu, M. Brooke
    An enhancement study on the SDSL upstream receiver. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:442-445 [Conf]
  555. Yao-Lin Jiang, Richard M. M. Chen, Omar Wing
    A waveform relaxation approach to determining periodic responses of linear differential-algebraic equations. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:443-446 [Conf]
  556. Y. Yedevelly, Kwong-Shu Chao, Lieyi Fang
    A compensation technique for integrator's pole error in cascaded sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:444-447 [Conf]
  557. M. Baroncini, Pisana Placidi, Andrea Scorzoni, G. C. Cardinali, L. Dori, S. Nicoletti
    Accurate extraction of the temperature of the heating element in micromachined gas sensors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:445-448 [Conf]
  558. Chung-Jr Lian, Kuan-Fu Chen, Hong-Hui Chen, Liang-Gee Chen
    Lifting based discrete wavelet transform architecture for JPEG2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:445-448 [Conf]
  559. Ming-Hwa Sheu, Ho En Liao, Shih Tsung Kan, Ming-Der Shieh
    A novel adaptive algorithm and VLSI design for frequency detection in noisy environment based on adaptive IIR filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:446-449 [Conf]
  560. Akio Ushida, Yoshihiro Yamagami, Ikkei Kinouchi, Yoshifumi Nishio, Yasuaki Inoue
    An efficient algorithm for finding multiple DC solutions based on Spice oriented Newton homotopy method. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:447-450 [Conf]
  561. Omid Oliaei
    Analysis of multirate sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:448-451 [Conf]
  562. D. K. Misra, D. Eungdamrong
    Coaxial aperture electrical sensor and its application-a tutorial overview. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:449-452 [Conf]
  563. T. Enomoto, A. Kotabe
    A fast motion estimation algorithm and low-power 0.13-um CMOS motion estimation circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:449-452 [Conf]
  564. T. Magesacher, Per Ödling, T. Nordstrom, T. Lunberg, M. Isaksson, Per Ola Börjesson
    An adaptive mixed-signal narrowband interference canceller for wireline transmission systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:450-453 [Conf]
  565. Mark Zwolinski, R. W. Allen
    Practical algorithms for fully decoupled mixed-mode simulation of electronic circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:451-454 [Conf]
  566. E. de Lira Mendes, Patrick Loumeau, Jean-François Naviner
    A switched-current sample and hold circuit for low frequency applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:452-455 [Conf]
  567. Jiangfeng Wu, L. Richard Carley
    A simulation study of electromechanical delta-sigma modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:453-456 [Conf]
  568. Savant Karunaratne, Hong Yan
    Techniques for modelling and training multimedia expressive talking heads. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:453-456 [Conf]
  569. A. N. L. Chan, K. W. H. Ng, J. M. C. Wong, H. C. Luong
    A 1-V 2.4-GHz CMOS RF receiver front-end for Bluetooth application. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:454-457 [Conf]
  570. K. Folkesson, C. Svensson, Jan-Erik Eklund
    Modeling of dynamic errors in algorithmic A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:455-458 [Conf]
  571. Bingxin Li, Hannu Tenhunen
    Sigma delta modulators using semi-uniform quantizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:456-459 [Conf]
  572. Jinghong Chen, Sung-Mo Kang
    Model-order reduction of nonlinear MEMS devices through arclength-based Karhunen-Loeve decomposition. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:457-460 [Conf]
  573. Dae Won Kim, Taek Won Kwon, Jung Min Seo, Jae Kun Yu, Kyu Lee, Jung Hee Suk, Jun Rim Choi
    A compatible DCT/IDCT architecture using hardwired distributed arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:457-460 [Conf]
  574. Risto Kaunisto, P. Korpi, J. Kiraly, Kari Halonen
    A linear-control wide-band CMOS attenuator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:458-461 [Conf]
  575. Z. Mu
    Simulation and modeling of power and ground planes in high speed printed circuit boards. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:459-462 [Conf]
  576. Christian Jesús B. Fayomi, Gordon W. Roberts, Mohamad Sawan
    A 1-V, 10-bit rail-to-rail successive approximation analog-to-digital converter in standard 0.18 um CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:460-463 [Conf]
  577. J. Vuolevi, T. Rahkonen
    Extracting a polynomial ac FET model with thermal couplings from S-parameter measurements. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:461-464 [Conf]
  578. Jae-Woo Ahn, Soo-Mook Moon, Wonyong Sung
    Feedback-directed memory disambiguation for embedded multimedia VLIW computing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:461-464 [Conf]
  579. Luca Fanucci, G. D'Angelo, A. Monterastelli, M. Paparo, B. Neri
    Fully integrated low-noise-amplifier with high quality factor L-C filter for 1.8 GHz wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:462-465 [Conf]
  580. Kevin T. Tang, Eby G. Friedman
    Estimation of transient voltage fluctuations in the CMOS-based power distribution networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:463-466 [Conf]
  581. Francisco Colodro Ruiz, Antonio Jesús Torralba Silgado
    Improved multirate sigma-delta architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:464-467 [Conf]
  582. J. S. Mao, Wu-Sheng Lu, S. C. Chan, Andreas Antoniou
    Design and multiplierless implementation of two-channel biorthogonal IIR filter banks with low system delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:465-468 [Conf]
  583. J. Scott
    Reconciliation of methods for bipolar transistor thermal resistance extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:465-468 [Conf]
  584. J. C. Huang, Ro-Min Weng, Cheng-Chih Chang, Kang Hsu, Kun-Yi Lin
    A 2 V 2.4 GHz fully integrated CMOS LNA. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:466-469 [Conf]
  585. Chih-Yang Hsu, Chaur-Wen Wei, Wen-Zen Shen
    A pattern compaction technique for power estimation based on power sensitivity information. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:467-470 [Conf]
  586. Baiying Yu, W. C. Black Jr.
    Error analysis for time-interleaved analog channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:468-471 [Conf]
  587. T. Karp, A. Mertins
    Implementation of biorthogonal cosine-modulated filter banks with fixed-point arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:469-472 [Conf]
  588. Dietrich Fränken, Karlheinz Ochs
    Wave digital simulation of nonlinear electrical networks by means of passive Runge-Kutta methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:469-472 [Conf]
  589. Adiseno, M. Ismail, H. K. Olsson
    Dual-loop cross-coupled feedback amplifier for low-IF integrated receiver architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:470-473 [Conf]
  590. Heng-Liang Huang, Yeong-Ren Chen, Jing-Yang Jou, Wen-Zen Shen
    Grouped input power sensitive transition an input sequence compaction technique for power estimation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:471-474 [Conf]
  591. C. Beainy, Rola A. Baki, Mourad N. El-Gamal
    Distortion analysis of high-frequency log-domain filters using Volterra series. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:472-475 [Conf]
  592. Her-Chang Chao
    A new approach to design of two-channel filter banks with PR and low-delay. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:473-476 [Conf]
  593. Dietrich Fränken, Karlheinz Ochs
    Numerical stability properties of passive Runge-Kutta methods. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:473-476 [Conf]
  594. Mohamed A. Elgamel, Ahmed M. Shams, Xi Xueling, Magdy A. Bayoumi
    Enhanced low power motion estimation VLSI architectures for video compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:474-477 [Conf]
  595. N. Nastos, Yannis Papananos
    A CAD tool for benchmarking MOSFET models. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:475-478 [Conf]
  596. Jorge R. Fernandes, Michiel H. L. Kouwenhoven, Chris van den Bos
    The effect of mismatch and disturbances on the quadrature relation of a cross-coupled relaxation oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:476-479 [Conf]
  597. A. Mertins
    Boundary filters with maximum coding gain and ideal DC behavior for size-limited paraunitary filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:477-480 [Conf]
  598. R. Pieper, S. Michael
    Considerations for predicting freezeout and exhaustion under a variety of nontrivial conditions. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:477-480 [Conf]
  599. Erno Salminen, Timo D. Hämäläinen, Tero Kangas, Kimmo Kuusilinna, Jukka Saarinen
    Interfacing multiple processors in a system-on-chip video encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:478-481 [Conf]
  600. K. S. Karim, P. Servati, N. Mohan, Arokia Nathan, John A. Rowlands
    VHDL-AMS modeling and simulation of a passive pixel sensor in a-Si: H technology for medical imaging. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:479-482 [Conf]
  601. Arie van Staveren, Chris J. M. Verhoeven
    Optimizing a resonator tap for maximizing oscillator carrier-to-noise ratio. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:480-483 [Conf]
  602. David B. H. Tay
    Least squares design of the class of triplet halfband filter banks. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:481-484 [Conf]
  603. Luigi Occhipinti, G. Spoto, M. Branciforte, F. Doddo
    Defects detection and characterization by using cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:481-484 [Conf]
  604. Konstantina Karagianni, Thanos Stouraitis
    A vector processor for 3-D geometrical transformations. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:482-485 [Conf]
  605. Manuel J. Bellido, Jorge Juan-Chico, Paulino Ruiz-de-Clavijo, Antonio J. Acosta, Manuel Valencia
    Gate-level simulation of CMOS circuits using the IDDM model. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:483-486 [Conf]
  606. A. Rezayee, K. Martin
    A three-stage coupled ring oscillator with quadrature outputs. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:484-487 [Conf]
  607. K. Slavakis, I. Yamada
    Compactly supported matrix valued wavelets-biorthogonal unconditional bases. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:485-488 [Conf]
  608. V. Bonaiuto, A. Maffucci, G. Miano, M. Salerno, F. Sargeni, P. Serra, C. Visone
    Hardware implementation of a CNN for analog simulation of reaction-diffusion equations. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:485-488 [Conf]
  609. Stefan Getzlaff, Jörg Schreiter, Achim Graupner, René Schüffny
    A system-on-chip realization of a CMOS image sensor with programmable analog image preprocessing. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:486-489 [Conf]
  610. W. H. Kao, Ch-Yuan Lo, R. Singh, M. Basel
    Parasitic extraction: current state of the art and future trends. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:487-490 [Conf]
  611. Kari Stadius, Risto Kaunisto, Veikko Porra
    Monolithic tunable capacitors for RF applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:488-491 [Conf]
  612. David B. H. Tay
    Balanced spatial and frequency localised 2-D nonseparable wavelet filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:489-492 [Conf]
  613. B. D. Calvert
    Hopfield networks with an infinite number of cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:489-492 [Conf]
  614. P. Dudek, P. J. Hicks
    An analogue SIMD focal-plane processor array. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:490-493 [Conf]
  615. Wei-Hsin Chang, Shuenn-Der Tzeng, Chen-Yi Lee
    A novel subcircuit extraction algorithm by recursive identification scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:491-494 [Conf]
  616. R. Perigny, Un-Ku Moon, Gabor C. Temes
    Area efficient CMOS charge pump circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:492-495 [Conf]
  617. Eduardo Cardoso Jr., Eduardo A. B. da Silva
    Design of non-linear multi-resolution decompositions with applications to image compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:493-496 [Conf]
  618. Radu Dogaru, Pedro Julián, Leon O. Chua
    A robust and efficient universal CNN cell circuit using simplicial neuro-fuzzy inferences for fast image processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:493-496 [Conf]
  619. Roberto Canegallo, D. Dozza, Roberto Guerrieri
    Low power techniques for flash memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:494-497 [Conf]
  620. Q. Li, Sung-Mo Kang
    Trapezoid-to-simple polygon recomposition for resistance extraction. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:495-498 [Conf]
  621. Eduard Alarcón, Alberto Poveda, Eva Vidal, Herminio Martínez
    Analog current-mode implementation of a one-cycle integrated controller for switching power converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:496-499 [Conf]
  622. Peter H. Bauer, Mihail L. Sichitiu, Kamal Premaratne
    Stability of 2-D distributed processes with time-variant communication delays. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:497-500 [Conf]
  623. Mika Laiho, Ari Paasio, Asko Kananen, Kari Halonen
    Discrete time analog polynomial type CNN with digital state. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:497-500 [Conf]
  624. M. Jagasivamani, Dong Sam Ha
    Development of a low-power SRAM compiler. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:498-501 [Conf]
  625. Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
    ESD design rule checker. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:499-502 [Conf]
  626. Eduard Alarcón, A. Romero, Alberto Poveda, Sonia Porta, Luis Martinez-Salamero
    Sliding-mode control analog integrated circuit for switching DC-DC power converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:500-503 [Conf]
  627. S. Saito, M. Kawamata
    Statistical sensitivity and minimum sensitivity structures of 2-D separable-denominator digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:501-504 [Conf]
  628. Matthew A. Clapp, Ralph Etienne-Cummings
    A dual pixel-type imager for imaging and motion centroid localization. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:501-504 [Conf]
  629. William Fornaciari, Donatella Sciuto, Cristina Silvano, Vittorio Zaccaria
    Fast system-level exploration of memory architectures driven by energy-delay metrics. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:502-505 [Conf]
  630. Q. Li, Yoonjong Huh, Jau-Wen Chen, Peter Bendix, Sung-Mo Kang
    Full chip ESD design rule checking. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:503-506 [Conf]
  631. Hongchin Lin, Nai-Hsien Chen
    New four-phase generation circuits for low-voltage charge pumps. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:504-507 [Conf]
  632. Ayuko Takagi, Kiyoshi Nishikawa, Hitoshi Kiya
    Low-bit motion estimation with edge enhanced images for lowpower MPEG encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:505-508 [Conf]
  633. Eugenio Culurciello, Ralph Etienne-Cummings, Kwabena Boahen
    High dynamic range, arbitrated address event representation digital imager. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:505-508 [Conf]
  634. A. Turier, L. Ben Ammar, A. Amara
    Static power consumption management in CMOS memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:506-509 [Conf]
  635. Daniel Eckerbert, Per Larsson-Edefors
    Cycle-true leakage current modeling for CMOS gates. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:507-510 [Conf]
  636. R. Balczewski, Ramesh Harjani
    Capacitive voltage multipliers: a high efficiency method to generate multiple on-chip supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:508-511 [Conf]
  637. M. W. Ng, Y. H. Chee, Y. P. Xu, G. Karunasiri
    On-chip compensation of dark current in infrared focal plane arrays. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:509-512 [Conf]
  638. Yi-Ching Liaw, Winston Lo, Jim Z. C. Lai
    Image restoration of JPEG coded images using mean removed classified vector quantization. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:509-512 [Conf]
  639. Byung-Do Yang, Lee-Sup Kim
    A low power charge-recycling ROM architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:510-513 [Conf]
  640. A. Maxim, M. Gheorghe
    A novel physical based model of deep-submicron CMOS transistors mismatch for Monte Carlo SPICE simulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:511-514 [Conf]
  641. José Luis González, Eduard Alarcón
    Clock-jitter induced distortion in high speed CMOS switched-current segmented digital-to-analog converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:512-515 [Conf]
  642. J. Zhang, E. C. Kulasekere, Kamal Premaratne, Peter H. Bauer
    Resource management of task oriented distributed sensor networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:513-516 [Conf]
  643. Roy L. Adler, Bruce Kitchens, Marco Martens, A. Nogueira, C. Tresser, Chai Wah Wu
    Error bounds for error diffusion and related digital halftoning algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:513-516 [Conf]
  644. Kah-Howe Tan, Wen Fung-Leong, S. Kadam, Michael A. Soderstrand, Louis G. Johnson
    Public-domain Matlab program to generate highly optimized VHDL for FPGA implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:514-517 [Conf]
  645. M. Karam, W. Fikry, H. Haddara, H. Ragai
    Implementation of hot-carrier reliability simulation in Eldo. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:515-518 [Conf]
  646. Jesper Steensgaard
    High-resolution mismatch-shaping digital-to-analog converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:516-519 [Conf]
  647. Apisak Worapishet, S. Ninyawee
    Magnetically-coupled tuneable inductor for wide-band variable frequency oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:517-520 [Conf]
  648. Y. Abe
    Digital halftoning with optimized dither array. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:517-520 [Conf]
  649. Li-minn Ang, Hon Nin Cheung
    Hardware implementation of the depth first search bit stream SPIHT system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:518-521 [Conf]
  650. Po-Xun Chiu, Yu-Chung Lin, Yi-Ling Hsieh, Tsai-Ming Hsieh
    Low power driven re-synthesis algorithm for heterogeneous FPGA under delay constraint. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:519-522 [Conf]
  651. Jiandong Jiang, E. K. F. Lee
    Segmented sine wave digital-to-analog converters for frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:520-523 [Conf]
  652. Alessandra Giovanardi, Gianluca Mazzini
    Frequency domain chaotic watermarking. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:521-524 [Conf]
  653. A. Massarini, U. Reggiani
    An efficient algorithm for the formulation of state equations and output equations for networks with ideal switches. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:521-524 [Conf]
  654. Ju Byoung Kim, Young Jin Lim, Moon Ho Lee
    A low complexity FEC design for DAB. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:522-525 [Conf]
  655. Shanq-Jang Ruan, Jen-Chiun Lin, Po-Hung Chen, Kun-Lin Tsai, Feipei Lai
    Synthesis of partition-codec architecture for low power and small area circuit design. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:523-526 [Conf]
  656. Mark Vesterbacka, J. Jacob Wikner
    Design of encoders for linear-coded D/A converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:524-527 [Conf]
  657. Hüseyin Özkaramanli, Asim Bhatti, Bulent Bilgehan
    Multi-wavelets from spline super-functions with approximation order. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:525-528 [Conf]
  658. A. Gandelli, S. Leva
    Haar state equations for power electronics system modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:525-528 [Conf]
  659. S. L. Toral, J. M. Quero, M. E. Perez, Leopoldo García Franquelo
    A microprocessor based system for ECG telemedicine and telecare. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:526-529 [Conf]
  660. J. Sosa, Juan A. Montiel-Nelson, Saeid Nooshabadi
    Efficient computation of the area/power consumption versus delay tradeoff curve for circuit critical path optimization. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:527-530 [Conf]
  661. Samgsuk Kim, Minkyu Song
    An 8-bit 200 MSPS CMOS A/D converter for analog interface module of TFT-LCD driver. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:528-531 [Conf]
  662. Itsda Boonyaroonate, S. Mori
    Compact DC/AC inverter for large electroluminescent lamp. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:529-532 [Conf]
  663. Jer-Min Jou, Yeu-Horng Shiau, Chin-Chi Liu
    Efficient VLSI architectures for the biorthogonal wavelet transform by filter bank and lifting scheme. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:529-532 [Conf]
  664. Kuan-Hung Chen, Shi-Chung Chang, Tzi-Dar Chiueh, Peter B. Luh, Xing Zhao
    SIMD architecture for job shop scheduling problem solving. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:530-533 [Conf]
  665. Imed Ben Dhaou, N. Money, Hannu Tenhunen
    Fast low-power characterization of arithmetic units in DSM CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:531-534 [Conf]
  666. Jirayuth Mahattanakul, Sitthichai Pookaiyaudom, Chris Toumazou
    Understanding Wilson current mirror via the negative feedback approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:532-535 [Conf]
  667. D. J. Kessler, Marian K. Kazimierczuk
    Power losses and efficiency of class E RF power amplifiers at any duty cycle. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:533-536 [Conf]
  668. Elizabeth Elias, Per Löwenborg, Håkan Johansson, Lars Wanhammar
    Tree-structured IIR/FIR octave-band filter banks with very low-complexity analysis filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:533-536 [Conf]
  669. Chun-Yueh Huang, Gwo-Jeng Yu, Bin-Da Liu
    A hardware design approach for merge-sorting network. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:534-537 [Conf]
  670. Yi-Jong Yeh, Sy-Yen Kuo
    An optimization-based low-power voltage scaling technique using multiple supply voltages. [Citation Graph (0, 0)][DBLP]
    ISCAS (5), 2001, pp:535-538 [Conf]
  671. Huiting Chen, F. Whiteside, Randall L. Geiger
    Current mirror circuit with accurate mirror gain for low beta transistors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:536-539 [Conf]
  672. Marian K. Kazimierczuk, A. J. Edstrom, Alberto Reatti
    Buck PWM DC-DC converter with reference-voltage-modulation feedforward control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:537-540 [Conf]
  673. L. Lin, W. H. Holmes, E. Ambikairajah
    Auditory filter bank inversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:537-540 [Conf]
  674. Pui-Lam Siu, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
    A low power asynchronous DES. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:538-541 [Conf]
  675. L. Toth, Yannis P. Tsividis
    Generalized chopper stabilization. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:540-543 [Conf]
  676. Xiao Fan Wang, Guanrong Chen, Kim Fung Man
    Making a stable discrete-time system chaotic via small-amplitude output feedback. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:541-544 [Conf]
  677. C. W. Kok, Yingbo Hua, J. H. Manton
    A nonuniform filterbank structure for channel precoding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:541-544 [Conf]
  678. Chang-Ki Kwon, Kwyro Lee
    Reconfigurable and programmable minimum distance search engine for portable video compression systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:542-545 [Conf]
  679. Chunyan Wang, M. Omair Ahmad, M. N. S. Swamy
    Low power current comparator cell for weak current operations. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:544-547 [Conf]
  680. Takao Hinamoto
    A novel local state-space model for 2-D digital filters and its properties. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:545-548 [Conf]
  681. Yong Feng, Xinghuo Yu, Zhihong Man
    Non-singular terminal sliding mode control and its application for robot manipulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:545-548 [Conf]
  682. K. Rajagopalan, P. Sutton
    A flexible multiplication unit for an FPGA logic block. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:546-549 [Conf]
  683. S. Takagi, N. R. Agung, K. Wada, N. Fujii
    Active guard band circuit for substrate noise suppression. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:548-551 [Conf]
  684. E. N. Sanchez, J. P. Perez, G. Chen
    Chaos reproduction by dynamic neural networks: an inverse optimal control approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:549-552 [Conf]
  685. W.-S. Lu
    Design of 2-D FIR filters with power-of-two coefficients: a semidefinite programming relaxation approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:549-552 [Conf]
  686. Aiman H. El-Maleh, Yahya E. Osais
    A retiming-based test pattern generator design for built-in self test of data path architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:550-553 [Conf]
  687. Wooyoung Choi, Ramesh Harjani, Bapiraju Vinnakota
    Non-ideal amplifier effects on the accuracy of analog-to-digital capacitor ratio converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:552-555 [Conf]
  688. P. van der Kloet, F. L. Neerhoff
    Modal factorization of time-varying models for nonlinear circuits by the Riccati transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:553-556 [Conf]
  689. Wu-Sheng Lu, Andreas Antoniou
    A new method for the design of stable IIR 2-D digital filters using sequential semidefinite programming. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:553-556 [Conf]
  690. V. K. Jain
    Hybrid wavelet/spread-spectrum system for broadband wireless LANs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:554-557 [Conf]
  691. Rabin Raut
    Stabilizing the transconductance in CMOS transconductors for application in gm-C filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:556-559 [Conf]
  692. Derong Liu, A. Molchanov
    Robust stability of a class of nonlinear time-varying discrete systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:557-560 [Conf]
  693. Seo-How Low, Yong Ching Lim
    Multi-stage approach for the design of 2-D half-band filters using the frequency response masking technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:557-560 [Conf]
  694. Chien-Fang Hsu, Yuan-Hao Huang, Tzi-Dar Chiueh
    Design of an OFDM receiver for high-speed wireless LAN. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:558-561 [Conf]
  695. Robert M. Fox, H. J. Ko, William R. Eisenstadt
    High-gain common-mode feedback circuits for differential log-domain filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:560-563 [Conf]
  696. C. K. S. Pun, S. C. Chan, K. L. Ho
    Efficient 1D and circular symmetric 2D FIR filters with variable cutoff frequencies using the Farrow structure and multiplier-block. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:561-564 [Conf]
  697. T. Yamasaki, T. Shibata
    An analog similarity evaluation circuit featuring variable functional forms. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:561-564 [Conf]
  698. A. Dhammika S. Jayalath, Chintha Tellambura
    Peak-to-average power ratio reduction of an OFDM signal using data permutation with embedded side information. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:562-565 [Conf]
  699. S. Tantry, T. Yoneyama, H. Asai
    Two floating resistor circuits and their applications to synaptic weights in analog neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:564-567 [Conf]
  700. P. Persson, S. Nordebo, I. Claesson
    Design of digital filters with general hardware constraints by mean field annealing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:565-568 [Conf]
  701. T. Nakaguchi, K. Jin'no, M. Tanaka
    Hardware combinatorial optimization problems solver by hysteresis neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:565-568 [Conf]
  702. K. Sathananathan, Chintha Tellambura
    Forward error correction codes to reduce intercarrier interference in OFDM. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:566-569 [Conf]
  703. A. M. A. Ali, K. Nagaraj
    Correction of operational amplifier gain error in pipelined A/D converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:568-571 [Conf]
  704. H. Hikawa
    Digital pulse mode neural network with simple synapse multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:569-572 [Conf]
  705. Abbes Amira, Ahmed Bouridane, Peter Milligan
    An FPGA based Walsh Hadamard transforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:569-572 [Conf]
  706. Jinwen Shentu, J. Armstrong
    Blind frequency offset estimation for PCC-OFDM with symbols overlapped in the time domain. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:570-573 [Conf]
  707. J. B. Hughes, M. Mec, W. Donaldson
    A low voltage 8-bit, 40 MS/s switched-current pipeline analog-to-digital converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:572-575 [Conf]
  708. H. O. Johansson, M. Horowitz
    Sampling-rate optimization of an interleaved-sampling front-end. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:573-576 [Conf]
  709. Chun Lu, Bingxue Shi, Lu Chen
    A programmable on-chip BP learning neural network with enhanced neuron characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:573-576 [Conf]
  710. Lijun Gao, Keshab K. Parhi
    Custom VLSI design of efficient low latency and low power finite field multiplier for Reed-Solomon codec. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:574-577 [Conf]
  711. Babak Nejati, Omid Shoaei
    A 10-bit, 2.5-V, 40 M sample/s, pipelined analog-to-digital converter in 0.6-um CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:576-579 [Conf]
  712. Gianfranco Avitabile, B. Chellini, G. Fedi, Antonio Luchetta, Stefano Manetti
    A neural architecture for the parameter extraction of high frequency devices [MMICs]. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:577-580 [Conf]
  713. Mokhtar Nibouche, Ahmed Bouridane, Omar Nibouche, Danny Crookes
    Rapid prototyping of orthonormal wavelet transforms on FPGAs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:577-580 [Conf]
  714. Chiou-Yng Lee, Erl-Huei Lu, Jau-Yien Lee
    New bit-parallel systolic multipliers for a class of GF(2m). [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:578-581 [Conf]
  715. Yong-In Park, S. Karthikeyan, F. Tsay, E. Bartolome
    A low power 10 bit, 80 MS/s CMOS pipelined ADC at 1.8 V power supply. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:580-583 [Conf]
  716. Hazem M. El-Bakry
    Fast iris detection for personal identification using modular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:581-584 [Conf]
  717. Kaamran Raahemifar, J. Ahmadi
    An efficient 0-1 linear programming for optimal PLA folding. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:581-584 [Conf]
  718. Sung-Won Lee, In-Cheol Park
    A low-power variable length decoder based on successive decoding of shoft codewords. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:582-585 [Conf]
  719. Lauri Sumanen, Kari Halonen
    A single-amplifier 6-bit CMOS pipeline A/D converter for WCDMA receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:584-587 [Conf]
  720. Sabri Arik, Vedat Tavsanoglu
    Further results on the global asymptotic stability of neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:585-588 [Conf]
  721. Soo-Chang Pei, Min-Hung Yeh
    A novel method for discrete fractional Fourier transform computation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:585-588 [Conf]
  722. Mohammad K. Ibrahim, A. Almulhem
    Bit-level pipelined digit serial GF(2m) multiplier. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:586-589 [Conf]
  723. Dalibor Biolek, Viera Biolkova
    Algorithmic s-z transformations for continuous-time to discrete-time filter conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:588-590 [Conf]
  724. T. Sakaue, M. Matsuzaki, M. Miyata
    On the stability of bilayer associative memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:589-591 [Conf]
  725. Liang Tao, Hon Keung Kwan
    Real-valued discrete Gabor transform for image representation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:589-592 [Conf]
  726. Abdoul Rjoub, M. Alrousan, O. Jarrah, Odysseas G. Koufopavlou
    Multi-level low swing voltage values for low power design applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:590-593 [Conf]
  727. R. H. Klunder, J. Hoekstra
    Energy conservation in a circuit with single electron tunnel junctions. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:591-594 [Conf]
  728. William Soares-Filho, José Manoel de Seixas, Luiz Pereira Calôba
    Principal component analysis for classifying passive sonar signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:592-595 [Conf]
  729. Håkan Johansson, Per Löwenborg
    Reconstruction of nonuniform sampled bandlimited signals using digital fractional filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:593-596 [Conf]
  730. P. R. van der Meer, Arie van Staveren
    Effectivity of standby-energy reduction techniques for deep sub-micron CMOS. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:594-597 [Conf]
  731. N. Nayak, Baiying Yu, W. C. Black Jr.
    A comparison of transient digitization methods for high speed analog signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:595-598 [Conf]
  732. Joachim Neves Rodrigues, Viktor Öwall, Leif Sörnmo
    QRS detection for pacemakers in a noisy environment using a time lagged artificial neural network. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:596-599 [Conf]
  733. C. W. Kok, K. Yoneyama, M. Ikehara
    Symmetric extension for finite length multirate signal processing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:597-600 [Conf]
  734. T. R. Yasuda, M. Yamamoto, T. Nishi
    A power-on reset pulse generator for low voltage applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:599-601 [Conf]
  735. Igor M. Filanovsky, P. N. Matkhanov
    On synthesis of a network to have the impulse response described by an integer power of sinusoid over its semi-period. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:599-602 [Conf]
  736. S. Lesueur, Daniel Massicotte, P. Sicard
    Indirect inverse adaptive control based on neural networks using dynamic back propagation for nonlinear dynamic systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:600-603 [Conf]
  737. Per Löwenborg, Håkan Johansson
    Quantization noise in filter bank analog-to-digital converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:601-604 [Conf]
  738. R. Becker
    Control loop for optimization of power consumption in VLSI designs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:602-605 [Conf]
  739. Igor M. Filanovsky, P. N. Matkhanov
    On synthesis of a reactance network having the step response described by a sinusoid with a given envelope. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:603-606 [Conf]
  740. J. K. Satapathy, C. J. Harris
    A pseudo-adaptive fuzzy controller using hybrid T-operator concept. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:604-607 [Conf]
  741. T. W. Fox, L. E. Turner
    The design of peak constrained least squares FIR filters with low complexity finite precision coefficients. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:605-608 [Conf]
  742. Byung G. Jo, J. Y. Kang, Myung Hoon Sunwoo
    A low power and area efficient FIR filter chip for PRML read channels. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:606-609 [Conf]
  743. Piero Malcovati, Franco Maloberti
    Optimization of the integrator output swing in low-voltage sigma-delta modulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:607-610 [Conf]
  744. Y. Uchiyama, Miki Haseyama, Hideo Kitajima
    Hopfield neural networks for edge detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:608-611 [Conf]
  745. Yong Lian
    A new frequency-response masking structure with reduced complexity for FIR filter design. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:609-612 [Conf]
  746. Lai-Kan Leung, Cheong-fat Chan, Oliver Chiu-sing Choy
    A giga-hertz CMOS digital controlled oscillator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:610-613 [Conf]
  747. C. C. Ho, C. J. Kuo
    Oversampling sigma-delta modulator stabilized by two local nonlinear feedback loop techniques. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:611-614 [Conf]
  748. Cong-Kha Pham
    A novel synapses circuit and its application to a neural-based A/D converter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:612-615 [Conf]
  749. Luiz C. R. de Barcellos, Sergio L. Netto, Paulo S. R. Diniz
    Design of FIR filters combining the frequency-response masking and the WLS-Chebyshev approaches. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:613-616 [Conf]
  750. Kuo-Hsing Cheng, Wei-Bin Yang, Chun-Fu Chung
    A low-power high driving ability voltage control oscillator used in PLL. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:614-617 [Conf]
  751. Martijn F. Snoeij, Ovidiu Bajdechi, Johan H. Huijsing
    A 4th-order switched-capacitor sigma-delta A/D converter using a high-ripple Chebyshev loop filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:615-618 [Conf]
  752. Yifeng Zhang, Zhenya He, Chengjian Wei, Luxi Yang
    Cellular channel assignment using transient chaotic neural network with self-organizing pattern formation initializing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:616-619 [Conf]
  753. Andrzej Tarczynski
    FIR filters for systems with input clock jitter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:617-620 [Conf]
  754. T. Suutari, Jouni Isoaho, Hannu Tenhunen
    High-speed serial communication with error correction using 0.25 um CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:618-621 [Conf]
  755. Fernando Muñoz Chavero, Alfredo Perez VegaLeal, Ramón González Carvajal, Antonio B. Torralba, Jonathan Noel Tombs, Jaime Ramírez-Angulo
    A 1.1 V low-power Sigma-Delta modulator for 14-b 16 kHz A/D conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:619-622 [Conf]
  756. Farid Boussaïd, Amine Bermak, Abdesselam Bouzerdoum
    A wide dynamic range CMOS imager with extended shunting inhibition image processing capabilities. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:620-623 [Conf]
  757. Kei-Yong Khoo, Zhan Yu, Alan N. Willson Jr.
    Design of optimal hybrid form FIR filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:621-624 [Conf]
  758. U. Singh, M. Green
    New structures for very high-frequency CMOS clock dividers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:622-625 [Conf]
  759. Nguyen T. Thao
    Overview on a new approach to one-bit nth order Sigma-Delta modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:623-626 [Conf]
  760. Alberto Pesavento, Christof Koch
    A CMOS imager with focal-plane computation for feature detection. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:624-627 [Conf]
  761. Tian-Bo Deng
    Discretization-free design of variable fractional-delay FIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:625-628 [Conf]
  762. Antti Heiskanen, Antti Mäntyniemi, Timo Rahkonen
    A 30 MHz DDS clock generator with sub-ns time domain interpolator and -50 dBc spurious level. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:626-629 [Conf]
  763. Jader A. De Lima, C. Dualibe
    A low-voltage programmable-gain CMOS amplifier with very-low temperature-drift. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:627-630 [Conf]
  764. K. Wawryn, A. Mazurek
    Low power, current mode circuits for programmable neural network. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:628-631 [Conf]
  765. Rika Ito, Kenji Suyama, Ryuichi Hirabayashi
    Optimal design of FIR filter with discrete coefficients based on integer semi-infinite linear programs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:629-632 [Conf]
  766. Rui L. Aguiar, Dinis M. Santos
    Oscillatorless clock multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:630-633 [Conf]
  767. M. M. Amourah, Randall L. Geiger
    A high gain strategy with positive-feedback gain enhancement technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:631-634 [Conf]
  768. Yasuhiro Ohtsuka, I. Ohta, Kiyoharu Aizawa
    Programmable spatially variant multiresolution readout capability on a sensor focal plane. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:632-635 [Conf]
  769. H. Safiri, Majid Ahmadi, Graham A. Jullien, William C. Miller
    A novel approach based on genetic algorithm for pipelining of recursive filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:633-636 [Conf]
  770. Hong-Yi Huang, Teng-Neng Wang
    High-speed CMOS logic circuits in capacitor coupling technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:634-637 [Conf]
  771. Joseph Sylvester Chang, Bah-Hwee Gwee, Yong Seng Lon, Meng Tong Tan
    A novel low-power low-voltage Class D amplifier with feedback for improving THD, power efficiency and gain linearity. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:635-638 [Conf]
  772. Alexander Fish, Orly Yadid-Pecht
    CMOS current/voltage mode winner-take-all circuit with spatial filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:636-639 [Conf]
  773. Behrouz Nowrouzian, Arthur T. G. Fuller
    A novel approach to the design of higher-order Bode-type variable-amplitude wave-digital equalizers. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:637-640 [Conf]
  774. Mauro Olivieri, Alessandro Trifiletti
    An all-digital clock generator firm-core based on differential fine-tuned delay for reusable microprocessor cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:638-641 [Conf]
  775. Christian Jesús B. Fayomi, Mohamad Sawan, Gordon W. Roberts
    A design strategy for a 1-V rail-to-rail input/output CMOS opamp. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:639-642 [Conf]
  776. Robert L. Ewing, Hoda S. Abdel-Aty-Zohdy
    Domain distributed intelligent processing for information fuselets. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:640-643 [Conf]
  777. Bogdan J. Falkowski, Sudha Kannurao
    Strict avalanche criterion in Boolean functions-a spectral approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:641-644 [Conf]
  778. Hamid Mahmoodi-Meimand, Ali Afzali-Kusha
    Efficient power clock generation for adiabatic logic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:642-645 [Conf]
  779. A. Shankar, José Silva-Martínez, Edgar Sánchez-Sinencio
    A low voltage operational transconductance amplifier using common mode feedforward for high frequency switched capacitor circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:643-646 [Conf]
  780. Qi-Wei Ge, A. Tanaka
    On optimality of a two-processor scheduling for program nets with combined OR-nodes. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:644-647 [Conf]
  781. Li Ding 0002, Pinaki Mazumder, N. Srinivas
    A dual-rail static edge-triggered latch. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:645-648 [Conf]
  782. Natalia Kazakova, R. Sung, Nelson G. Durdle, Martin Margala, Julien Lamoureux
    Fast and low-power inner product processor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:646-649 [Conf]
  783. Cheng-Chung Hsu, Jieh-Tsorng Wu
    Highly linear 100 MHz CMOS programmable gain amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:647-650 [Conf]
  784. J. M. Quero, A. Guerrero, Leopoldo García Franquelo, M. Dominguez, I. Ameijeiras, L. Castaner
    Light source position microsensor. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:648-651 [Conf]
  785. Hsie-Chia Chang, Chen-Yi Lee
    An area-efficient architecture for Reed-Solomon decoder using the inversionless decomposed Euclidean algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:649-652 [Conf]
  786. Taek Won Kwon, Chang-Seok You, Won-Seok Heo, Yong-Kyu Kang, Jun Rim Choi
    Two implementation methods of a 1024-bit RSA cryptoprocessor based on modified Montgomery algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:650-653 [Conf]
  787. B. Wilson, M. Al-Gahtani
    Improved logarithmic converter based on a transconductance feedback amplifier. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:651-654 [Conf]
  788. Giuseppe Grassi, Eugenio Di Sciascio
    A new learning algorithm for pattern classification using cellular neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:652-655 [Conf]
  789. Vassilis Paliouras, Thanos Stouraitis
    Signal activity and power consumption reduction using the logarithmic number system. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:653-656 [Conf]
  790. Hsin-Fu Lo, Ming-Der Shieh, Chien-Ming Wu
    Design of an efficient FFT processor for DAB system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:654-657 [Conf]
  791. H. Schmid
    The current-feedback OTA. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:655-658 [Conf]
  792. H. Sekiya, Hirotaka Koizumi, Shinsaku Mori, Iwao Sasase
    FM/PWM control scheme on class DE inverter for keeping high power conversion efficiency. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:656-659 [Conf]
  793. M. Ziegler, M. Stan
    Optimal logarithmic adder structures with a fanout of two for minimizing the area-delay product. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:657-660 [Conf]
  794. Jiun-In Guo
    A low cost 2-D inverse discrete cosine transform design for image compression. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:658-661 [Conf]
  795. A. Hossein Nejad-Malayeri, T. Manku
    A 270 MHz, 1.8 V fully differential CMOS operational amplifier for switched capacitor channel select filters in wide-band wireless applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:659-662 [Conf]
  796. M. Criscione, Luigi Fortuna, A. Imbruglia, G. Scalia
    Fuzzy logic controlled monolithic switching regulator in BCD technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:660-663 [Conf]
  797. S. Miyagi, H. Sakai
    Performance comparison between the filtered-error LMS and the filtered-X LMS algorithms [ANC]. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:661-664 [Conf]
  798. Jiun-In Guo
    A new DA-based array for one dimensional discrete Hartley transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:662-665 [Conf]
  799. Andrew T. K. Tang
    Bandpass spread spectrum clocking for reduced clock spurs in autozeroed amplifiers. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:663-666 [Conf]
  800. Spartacus Gomaríz, Eduard Alarcón, Francesc Guinjoan, Enric Vidal-Idiarte, Luis Martinez-Salamero
    Two-rules-based boundary layer fuzzy controller for DC to DC switching regulators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:664-667 [Conf]
  801. Ricardo Merched, A. H. Sayed
    Extended fast fixed order RLS adaptive filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:665-668 [Conf]
  802. Maw-Ching Liu, Chien-Lung Chen, Ding-Yu Shin, Chin-Hung Lin, Shyh-Jye Jou
    Low-power multiplierless FIR filter synthesizer based on CSD code. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:666-669 [Conf]
  803. Eric A. M. Klumperink, F. Bruccoleri, Bram Nauta
    Finding all elementary circuits exploiting transconductance. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:667-670 [Conf]
  804. K. Howard, Marian K. Kazimierczuk
    Eddy-current power loss in laminated iron cores. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:668-671 [Conf]
  805. Ricardo Merched, A. H. Sayed
    RLS-Laguerre lattice adaptive filtering: error feedback and array-based algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:669-672 [Conf]
  806. Chin-Liang Wang, Ching-Hsien Chang
    A new memory-based FFT processor for VDSL transceivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:670-673 [Conf]
  807. Jaime Ramírez-Angulo, Ramón González Carvajal, Antonio Jesús Torralba Silgado, C. Nieva
    A new class AB differential input stage for implementation of low-voltage high slew rate op amps and linear transconductors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:671-674 [Conf]
  808. Nicola Femia, Giovanni Spagnuolo, Massimo Vitelli
    Generalized invariant models for the analysis of soft-switching cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:672-675 [Conf]
  809. Junibakti Sanubari, Keiichi Tokuda
    Fast convergence transversal adaptive filtering algorithm for impulsive environment based on T distribution assumption. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:673-676 [Conf]
  810. S. Michael, R. Pieper
    A VLSI implementation of a universal programmable low sensitivity sampled data filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:674-677 [Conf]
  811. R. Sitdhikorn, Apisak Worapishet, John B. Hughes
    A low-voltage neutralised class AB switched-current technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:675-678 [Conf]
  812. Janusz Biernacki, Dariusz Czarkowski
    High frequency transformer modeling. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:676-679 [Conf]
  813. Yuexian Zou, Shing-Chow Chan
    A robust quasi-Newton adaptive filtering algorithm for impulse noise suppression. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:677-680 [Conf]
  814. Milena Stankovic, Radomir S. Stankovic, Jaakko Astola, Karen O. Egiazarian
    Circuit realization of spectral transforms in Fibonacci interconnection topologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:678-681 [Conf]
  815. K. Michelakis, S. Despotopoulos, S. G. Badcock, C. Papavassiliou, A. G. O'Neill, Chris Toumazou
    SiGe HMOSFET differential pair. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:679-682 [Conf]
  816. Luigi Fortuna, Mattia Frasca, Alessandro Rizzo
    Generating solitons in lattices of nonlinear circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:680-683 [Conf]
  817. Meng Tong Tan, Joseph Sylvester Chang, Yit Chow Tong
    A novel low-voltage low-power wave digital filter bank for an intelligent noise reduction digital hearing instrument. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:681-684 [Conf]
  818. José M. Quintana, Maria J. Avedillo
    Reed-Muller descriptions of symmetric functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:682-685 [Conf]
  819. L. Toth, G. Palaskas, Yannis P. Tsividis
    "Noninvasive" techniques for syllabic companding in signal processors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:683-686 [Conf]
  820. Kenya Jin'no
    Analysis of hysteresis cellular automata. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:684-687 [Conf]
  821. Johnny Holmberg, Lennart Harnefors, Krister Landernäs, Svante Signell
    Computational properties of LDI/LDD lattice filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:685-688 [Conf]
  822. J. L. Cura, Rui L. Aguiar
    Dynamic range boosting for wireless optical receivers. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:686-689 [Conf]
  823. M. H. Capstick, J. K. Fidler
    Delay approximation for synchronous filter topologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:687-690 [Conf]
  824. S. Abbisso, Riccardo Caponetto, O. Diamante, Luigi Fortuna, D. Porto
    Non-integer order integration by using neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:688-691 [Conf]
  825. M. M. Al-Ibrahim
    A simple recursive digital sinusoidal oscillator with uniform frequency spacing. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:689-692 [Conf]
  826. K. Miyashita, Y. S. Ichikawa, Y. Nakao, N. Shimataka, T. Otuki
    110 MHz IF-baseband CMOS receiver for J-CDMA/AMPS application. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:690-693 [Conf]
  827. H. Babic, M. Vucic
    Filter families with minimum time-bandwidth products. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:691-694 [Conf]
  828. Chai Wah Wu
    Synchronization in arrays of coupled nonlinear systems: passivity circle criterion and observer design. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:692-695 [Conf]
  829. Hyeong-Ju Kang, In-Cheol Park
    Multiplier-less IIR filter synthesis algorithms to trade-off the delay and the number of adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:693-696 [Conf]
  830. Jonghae Kim, Ramesh Harjani
    An ISM band CMOS integrated transceiver design for wireless telemetry system. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:694-697 [Conf]
  831. Kahtan A. Mezher, P. Bowron
    Noise-flow-graph analysis of OTA-C filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:695-698 [Conf]
  832. F. Komatsu, Hiroyuki Torikai, Toshimichi Saito
    Various superstable synchronous phenomena in switch-coupled relaxation oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:696-699 [Conf]
  833. M. Bhattacharya, Jaakko Astola
    Multiplierless implementation of recursive digital filters based on coefficient translation methods in low sensitivity structures. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:697-700 [Conf]
  834. Jaeyoung Shin, Joongho Choi, Jinup Lim, Sungwon Noh, Namil Baek, Jong-Hyeong Lee
    A 3.3-V analog front-end chip for HomePNA applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:698-701 [Conf]
  835. N. Matsumoto
    Simple proof of the Routh stability criterion based on order reduction of polynomials and principle of argument. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:699-702 [Conf]
  836. X. Yu, Mehmet Önder Efe, Okyay Kaynak
    A backpropagation learning framework for feedforward neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:700-702 [Conf]
  837. Kiwon Choi, Minkyu Song
    Design of a high performance 32×32-bit multiplier with a novel sign select Booth encoder. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:701-704 [Conf]
  838. Jaeseo Lee, Jae-Won Lim, Sung-Jun Song, Sung-Sik Song, Wang-joo Lee, Hoi-Jun Yoo
    Design and implementation of CMOS LVDS 2.5 Gb/s transmitter and 1.3 Gb/s receiver for optical interconnections. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:702-705 [Conf]
  839. Ahmed Al-Ani, Mohamed Deriche
    A Dempster-Shafer theory of evidence approach for combining trained neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:703-706 [Conf]
  840. S. Hong, W. E. Stark
    Performance effects of using analog memory in baseband signal processing systems design. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:703-706 [Conf]
  841. Omar Nibouche, Ahmed Bouridane, Mokhtar Nibouche
    New architectures for serial-serial multiplication. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:705-708 [Conf]
  842. Ping Wu, Kai He
    A CMOS triple-band fractional-N frequency synthesizer for GSM/GPRS/EDGE applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:706-709 [Conf]
  843. Jaime Ramírez-Angulo, F. Ledesma
    Compact CMOS circuits for high-speed continuous-time linear weighted voltage addition. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:707-710 [Conf]
  844. M. Macda, H. Miyajima
    Properties of deletion methods in competitive learning. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:707-710 [Conf]
  845. Oscar Gustafsson, Henrik Ohlsson, Lars Wanhammar
    Minimum-adder integer multipliers using carry-save adders. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:709-712 [Conf]
  846. Yi-Chuan Liu, Chung-Cheng Wang, Terng-Yin Hsu, Chen-Yi Lee
    A wideband digital frequency synthesizer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:710-713 [Conf]
  847. M. Jiang, X. Yu
    Terminal attractor based back propagation learning for feedforward neural networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:711-714 [Conf]
  848. Joongho Choi, Jinup Lim, Sungwon Noh, Jaeyoung Shin, Kwangoh Kim
    3.3-V line drivers for digital subscriber line applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:711-714 [Conf]
  849. W. G. Natter, Behrouz Nowrouzian
    A novel multiplier recoding technique and its application to the development of a high-speed parallel online multiply-accumulate architecture. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:713-716 [Conf]
  850. Pietro Andreani
    A 1.8-GHz monolithic CMOS VCO tuned by an inductive varactor. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:714-717 [Conf]
  851. Spartacus Gomaríz, Eduard Alarcón, Francesc Guinjoan, Enric Vidal-Idiarte, Luis Martinez-Salamero
    Piecewise PWM-sliding global control of a boost switching regulator by means of first-order Takagi-Sugeno fuzzy control. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:715-718 [Conf]
  852. M. Ramezani, C. Andre T. Salama
    An improved bang-bang phase detector for clock and data recovery applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:715-718 [Conf]
  853. A. P. Preethy, Damu Radhakrishnan, Amos Omondi
    Fault-tolerance scheme for an RNS MAC: performance and cost analysis. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:717-720 [Conf]
  854. Ming-Ta Hsieh, J. Harvey, R. Harjani
    Power optimization of CMOS LC VCOs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:718-721 [Conf]
  855. C. K. L. Tam, Gordon W. Roberts
    A robust DC current generation and measurement technique for deep submicron circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:719-722 [Conf]
  856. M. A. Al-Saleh, M. Mir
    A low-cost digital simulator for performance evaluation of computer relays. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:719-722 [Conf]
  857. P. Sristi, Wu-Sheng Lu, Andreas Antoniou
    A new variable-step-size LMS algorithm and its application in subband adaptive filtering for echo cancellation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:721-724 [Conf]
  858. R. R.-B. Sheen, Oscal T.-C. Chen
    A CMOS PLL-based frequency synthesizer for wireless communication systems at 0.9, 1.8, 1.9 and 2.4 GHz. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:722-725 [Conf]
  859. S. L. Toral, J. M. Quero, Leopoldo García Franquelo
    SRC passivation controller implementation using stochastic computing. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:723-726 [Conf]
  860. S. S. Rajput, S. S. Jamuar
    Low voltage, low power, high performance current conveyors. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:723-726 [Conf]
  861. K. A. Mayyas, Tyseer Aboulnasr
    A stereophonic low complexity subband adaptive algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:725-728 [Conf]
  862. Panu Hämäläinen, Marko Hännikäinen, Timo Hämäläinen, Henk Corporaal, Jukka Saarinen
    Implementation of encryption algorithms on transport triggered architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:726-729 [Conf]
  863. Joerg Krupar, R. Srowik, Jörg Schreiter, Achim Graupner, René Schüffny, U. Jorges
    Minimizing charge injection errors in high-precision, high-speed SC-circuits. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:727-730 [Conf]
  864. Atsushi Kamo, Takayuki Watanabe, A. Asai
    Simulation for the optimal placement of decoupling capacitors on printed circuit board. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:727-730 [Conf]
  865. Masahide Abe, Masayuki Kawamata
    Comparison of convergence behavior of distributed evolutionary digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:729-732 [Conf]
  866. D. J. Soudris, M. M. Dasigenis, S. K. Vasilopoulou, Adonios Thanailakis
    A CAD tool for architecture level exploration and automatic generation of RNS converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:730-733 [Conf]
  867. Gianluca Giustolisi, Gaetano Palumbo
    Detailed frequency analysis of power supply rejection in Brokaw bandgap. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:731-734 [Conf]
  868. Chung-Chieh Fang
    Sampled-data poles and zeros of buck and boost converters. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:731-734 [Conf]
  869. Pedro D. Donate, C. Muravchik, Juan E. Cousseau
    Robust orthogonal adaptive deconvolution. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:733-736 [Conf]
  870. Yukio Mitsuyama, Zaldy Andales, Takao Onoye, Isao Shirakawa
    VLSI architecture of dynamically reconfigurable hardware-based cipher. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:734-737 [Conf]
  871. C. Busada, G. Bortolotto
    A switched controller for fast voltage fed parallel active filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:735-738 [Conf]
  872. Jader A. De Lima
    A low-voltage triode-MOSFET four-quadrant multiplier with optimized current-efficiency. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:735-738 [Conf]
  873. Isao Nakanishi, Yoshio Itoh, Yutaka Fukui
    Noise reduction system based on frequency domain adaptive filter using modified DFT pair. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:737-740 [Conf]
  874. S. Kawahitio, T. Eki, Y. Tadokoro
    A bit-serial column parallel processing architecture for on-sensor discrete Fourier transform. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:738-741 [Conf]
  875. Wensheng Yu, Long Wang
    Robust strictly positive real synthesis for convex combination of the fifth-order polynomials. [Citation Graph (0, 0)][DBLP]
    ISCAS (1), 2001, pp:739-742 [Conf]
  876. Daniel W. Berns, Jorge L. Moiola, Guangrong Chen
    A quasi-analytical method for period-doubling bifurcation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:739-742 [Conf]
  877. Artur Krukowski, Izzet Kale
    The design of arbitrary-band multi-path polyphase IIR filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:741-744 [Conf]
  878. Chris Howland, Andrew J. Blanksby
    Parallel decoding architectures for low density parity check codes. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:742-745 [Conf]
  879. X. Chen
    Bifurcation stabilization for nonlinear systems with double-zero eigenvalues. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:743-746 [Conf]
  880. Arthur T. G. Fuller, Behrouz Nowrouzian
    A novel technique for optimization over the canonical signed-digit number space using genetic algorithms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:745-748 [Conf]
  881. Jaesik Lee, Yoonjong Huh, Peter Bendix, Sung-Mo Kang
    Design-for-ESD-reliability for high-frequency I/O interface circuits in deep-submicron CMOS technology. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:746-749 [Conf]
  882. T. Hosakado, K. Okumura
    Algebraic representation of bifurcations in global parameter space with Grobner bases. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:747-750 [Conf]
  883. Artur Krukowski, Izzet Kale
    Constraint two-path polyphase IIR filter design using downhill simplex algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:749-752 [Conf]
  884. Edgar F. M. Albuquerque, Manuel M. Silva
    Evaluation of substrate noise in CMOS and low-noise logic cells. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:750-753 [Conf]
  885. Junji Kawata, Yoshifumi Nishio, Akio Ushida
    Bifurcation and complex phenomena in chaotic systems coupled by transmission line. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:751-754 [Conf]
  886. Chung J. Kuo, Souheil F. Odeh, M. C. Huang
    Image segmentation with improved watershed algorithm and its FPGA implementation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:753-756 [Conf]
  887. Ming-Dou Ker, Tung-Yang Chen, Chung-Yu Win
    ESD protection design in a 0.18-um salicide CMOS technology by using substrate-triggered technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:754-757 [Conf]
  888. Tetsushi Ueta, Shigeki Tsuji, Tetsuya Yoshinaga, Hiroshi Kawakami
    Calculation of the isocline for the fixed point with a specified argument of complex multipliers. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:755-758 [Conf]
  889. Michael Meißner, Michael C. Doggett, Urs Kanus, Johannes Hirche
    Accelerating volume rendering using an on-chip SRAM occupancy map. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:757-760 [Conf]
  890. Ming-Dou Ker, Tung-Yan Chen
    Design on the turn-on efficient power-rail ESD clamp circuit with stacked polysilicon diodes. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:758-761 [Conf]
  891. E. Lindberg, K. Murali, A. Tamasevicius
    Hyperchaotic circuit with damped harmonic oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:759-762 [Conf]
  892. Nikolaos D. Zervas, I. Tagopoulos, Vassilis Spiliotopoulos, Giorgos P. Anagnostopoulos, Dimitrios Soudris, Constantinos E. Goutis
    Performance comparison of DWT scheduling alternatives on programmable platforms. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:761-764 [Conf]
  893. I. Rovira, P. Sivonen, S. Rintamaki, M. Honkanen
    Highly linear TX IF-chip for multicarrier GSM 900 and 1800 base station. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:762-765 [Conf]
  894. K. Matsuda, Yoshihiko Horio, Kazuyuki Aihara
    A simulated LC oscillator using multi-input floating-gate MOSFETS. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:763-766 [Conf]
  895. Kuan-Fu Chen, Chung-Jr Lian, Hong-Hui Chen, Liang-Gee Chen
    Analysis and architecture design of EBCOT for JPEG-2000. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:765-768 [Conf]
  896. A. Maxim, B. Scott, E. Schneider, M. Hagge, S. Chacko, Dan Stiurca
    Sample-reset loop filter architecture for process independent and ripple-pole-less low jitter CMOS charge-pump PLLs. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:766-769 [Conf]
  897. Masayuki Yamauchi, Yoshifumi Nishio, Akio Ushida
    Reflection and transmission of phase-inversion-waves in oscillators coupled by two kinds of inductors. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:767-770 [Conf]
  898. L. Parolini, S. Bartoloni, Francesco Piazza
    Gabor expansion for stereophonic acoustic echo cancellation. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:769-772 [Conf]
  899. K. T. Christensen
    Design and optimization of CMOS switches for switched tuning of LC resonators. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:770-773 [Conf]
  900. L. Toth
    Analytical approach for the exact phase noise analysis of oscillators. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:771-774 [Conf]
  901. Ngai Wong, Tung-Sang Ng
    Improved roundoff noise performance in a direct-form IIR filter using a modified delta operator. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:773-776 [Conf]
  902. José Manuel de la Rosa, Maria Belen Pérez-Verdú, F. Medeiro, Rocio del Río, Ángel Rodríguez-Vázquez
    Analysis and experimental characterization of idle tones in 2nd-order bandpass Sigma-Delta modulators-a 0.8 um CMOS switched-current case study. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:774-777 [Conf]
  903. A. Vasylenko, Orla Feely
    Nonlinear dynamics of first-order DPLL with frequency-modulated input. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:775-778 [Conf]
  904. F. Rosati, Paolo Campolucci, Francesco Piazza
    Learning in linear and nonlinear multirate digital systems by signal flow graphs. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:777-780 [Conf]
  905. K. T. Tiew, A. J. Payne, Peter Y. K. Cheung
    MASH delta-sigma modulators for wideband and multi-standard applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:778-781 [Conf]
  906. F. L. Neerhoff, P. van der Kloet
    A complementary view on time-varying systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:779-782 [Conf]
  907. I-Hung Khoo, Hari C. Reddy, P. K. Rajan
    Delta operator based 2-D filter design using symmetry constraints. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:781-784 [Conf]
  908. Cheng-Chih Chang, Ro-Min Weng, J. C. Huang, Kang Hsu, Kun-Yi Lin
    A 1.5 V high gain CMOS mixer for 2.4-GHz applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:782-785 [Conf]
  909. A. M. Davis
    On the axiomatic foundations of circuit theory. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:783-786 [Conf]
  910. T. Harada, Mitsuji Muneyasu, Takao Hinamoto
    A pipeline architecture of quadratic adaptive Volterra filters based on NLMS algorithm. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:785-788 [Conf]
  911. Jackson Harvey, Ramesh Harjani
    Analysis and gain design of an integrated quadrature mixer with improved noise and image rejection. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:786-789 [Conf]
  912. Kit-Sang Tang, Kim-Fung Man, G. Chen
    Digitized n-scroll attractor model for secure communications. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:787-790 [Conf]
  913. Saman S. Abeysekera, Xue Yao
    A single stage decimator architecture for sigma-delta demodulators using Laguerre filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:789-792 [Conf]
  914. Sami Karvonen, Tom A. D. Riley, Juha Kostamovaara
    A low noise quadrature subsampling mixer. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:790-793 [Conf]
  915. M. Brucoli, D. Cafagna, L. Carnimeo
    Complete practical synchronization of hyperchaotic circuits via a scalar signal. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:791-794 [Conf]
  916. R. Martínez, A. Alvarez, P. Gómez, V. Nieto, V. Rodellar
    Combination of adaptive filtering and spectral subtraction for noise removal. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:793-796 [Conf]
  917. Chih-Chun Tang, Wen-Shih Lu, Lan-Da Van, Wu-Shiung Feng
    A 2.4-GHz CMOS down-conversion doubly balanced mixer with low supply voltage. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:794-797 [Conf]
  918. Jiu-chao Feng, C. K. Tse, Francis C. M. Lau
    A chaos tracker applied to non-coherent detection in chaos-based digital communication systems. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:795-798 [Conf]
  919. Christian S. Gargour, Venkat Ramachandran, Ravi P. Ramachandran
    Generation of a class of two-dimensional (2-D) transfer functions yielding variable magnitude and contour characteristics. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:797-800 [Conf]
  920. M. E. S. Elrabaa, Mohamed I. Elmasry
    Split-Gate Logic circuits for multi-threshold technologies. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:798-801 [Conf]
  921. P. Wagh
    Closed-form spectral analysis of pulse-width modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:799-802 [Conf]
  922. Mikko Valkama, Markku Renfors
    Second-order sampling of wideband signals. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:801-804 [Conf]
  923. Yiannis Moisiadis, A. I. Bouras, Angela Arapoyanni, Lampros Dermentzoglou
    A high-performance low-power static differential double edge-triggered flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:802-805 [Conf]
  924. Luigi Fortuna, Mattia Frasca, Alessandro Rizzo
    Chaos preservation through continuous chaotic pulse position modulation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:803-806 [Conf]
  925. Frank Dachselt, M. Gotz
    Rational cycle decoding algorithm for the first-order delta-sigma modulator. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:805-808 [Conf]
  926. Chulwoo Kim, Sung-Mo Kang
    A low-power reduced swing single clock flip-flop. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:806-809 [Conf]
  927. Federico Bizzarri, Marco Storace
    2-D bifurcation diagram of an oscillator based on PWL hysteresis. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:807-810 [Conf]
  928. Yegui Xiao, Naoko Tani
    Statistical properties of a memoryless nonlinear gradient algorithm for an adaptive constrained IIR notch filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:809-812 [Conf]
  929. Y. Fouzar, Yvon Savaria, Mohamad Sawan
    A new controlled gain phase-locked loop technique. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:810-813 [Conf]
  930. P. Ashwin, J. H. B. Deane, X.-C. Fu
    Dynamics of a bandpass sigma-delta modulator as a piecewise isometry. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:811-814 [Conf]
  931. Shotaro Nishimura, Aloys Mvuma, Takao Hinamoto
    Performance improvement of DS-SS communication systems using an adaptive IIR notch filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:813-816 [Conf]
  932. Ian Brynjolfson, Zeljko Zilic
    A new PLL design for clock management applications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:814-817 [Conf]
  933. T. Tsubone, K. Hoshino, T. Saito
    Bifurcation from a 3-D hysteresis piecewise-constant circuit. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:815-818 [Conf]
  934. Y. Kinugasa, J. Okello, Y. Itoh, Masaki Kobayashi, Y. Fukui
    A new algorithm for adaptive notch filter with sub-band filtering. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:817-820 [Conf]
  935. Takayuki Hamamoto, T. Wakamatsu, Kiyoharu Aizawa
    New method of on-sensor A/D conversion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:818-821 [Conf]
  936. F. Yuan, Kaamran Raahemifar, F. A. Mohammadi
    Efficient transient analysis of nonlinear circuits using Volterra series and piecewise constant interpolation. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:819-822 [Conf]
  937. J. Okello, Y. Kinugasa, Y. Itoh, Y. Fukui, Masaki Kobayashi
    A new unbiased online algorithm for equation error IIR ADF. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:821-824 [Conf]
  938. R. Bouchakour, N. Harabech, P. Canet, Ph. Boivin, J. M. Mirabel
    Modeling of a floating-gate EEPROM cell using a charge sheet approach including variable tunneling capacitance and polysilicon gate depletion effect. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:822-825 [Conf]
  939. Marco Storace, Pedro Julian, Mauro Parodi
    Towards the circuit implementation of the Hodgkin-Huxley neuron model: A PWL approach. [Citation Graph (0, 0)][DBLP]
    ISCAS (3), 2001, pp:823-826 [Conf]
  940. Henrik Ohlsson, Oscar Gustafsson, Lars Wanhammar
    Arithmetic transformations for increased maximal sample rate of bit-parallel bireciprocal lattice wave digital filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:825-828 [Conf]
  941. Huiyun Li, Bah-Hwee Gwee, Joseph Sylvester Chang
    A digital Class D amplifier design embodying a novel sampling process and pulse generator. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:826-829 [Conf]
  942. Yang Xiao
    Hurwitz-Schur stability test of interval bivariate polynomials. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:829-832 [Conf]
  943. Marco Ottavi, Gian-Carlo Cardarilli, P. Marinucci, Salvatore Pontarelli, Adelio Salsano
    Development of a dynamic routing system for a fault tolerant solid state mass memory. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:830-833 [Conf]
  944. Bin Jiao, Wei-Yong Yan, Z. Zang, S. Nordholm
    Analysis and synthesis of signal set with constrained magnitude spectrum. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:833-836 [Conf]
  945. Ye Lu, Mourad N. El-Gamal
    A 2.3 V low noise, low power, 10 GHz bandwidth Si-bipolar transimpedance preamplifier for optical receiver front-ends. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:834-837 [Conf]
  946. T. Hinamoto, T. Kouno
    Realization of state-estimate feedback controllers with minimum L 2-sensitivity. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:837-840 [Conf]
  947. Yngvar Berg, Snorre Aunet, Øivind Næss, Mats Høvin
    Exploiting sinh and tanh shaped ultra low-voltage floating-gate transconductance amplifiers to reduce harmonic distortion. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:838-841 [Conf]
  948. Venkat Ramachandran, Ravi P. Ramachandran, Christian S. Gargour
    Some properties of the z-domain continued fraction expansions of 1-D discrete reactance functions. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:841-844 [Conf]
  949. Tommy Kwong-Kin Tsang, Mourad N. El-Gamal
    A fully integrated 1 V 5.8 GHz bipolar LNA. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:842-845 [Conf]
  950. V. Winstead, B. R. Barmish
    A universal figure of merit for stochastic first order filters. [Citation Graph (0, 0)][DBLP]
    ISCAS (2), 2001, pp:845-848 [Conf]
  951. P. Caner, R. Bouchakour, N. Harabech, Ph. Boivin, J. M. Mirabel
    EEPROM programming study-time and degradation aspects. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:846-849 [Conf]
  952. S. I. Kayed, H. F. Ragaie, M. Abou El-Ela, F. A. S. Soliman
    VLSI design and implementation of analog CMOS 2nd generation current conveyors. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:850-853 [Conf]
  953. Yigang He, Yichuang Sun
    Fault isolation in nonlinear analog circuits with tolerance using the neural network-based L1-norm. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:854-857 [Conf]
  954. T. Ohira
    Emerging adaptive antenna techniques for wireless ad-hoc networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:858-861 [Conf]
  955. K. Gyoda, Y. Kado, Y. Ohno, K. Hasuike, T. Ohira
    WACNet - Wireless Ad-hoc Community Network. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:862-865 [Conf]
  956. T. Ogawa, E. Kudoh, H. Suda
    Multi-routing schemes for ad-hoc wireless networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:866-869 [Conf]
  957. Hongjun Xu, Kyung Sup Kwak
    Space-time block coding for wireless ad hoc networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:870-873 [Conf]
  958. Hiroshi Tamura, T. Moriyama, N. Matsumoto, Masakazu Sengoku, K. Mase, Shoji Shinoda
    Routing algorithms on wireless multihop networks and their modifications. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:874-877 [Conf]
  959. Y. Dumonteix, Y. Bajot, H. Mehrez
    A fast and low-power distance computation unit dedicated to neural networks, based on redundant arithmetic. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:878-881 [Conf]
  960. Chulwoo Kim, Kiwook Kim, Sung-Mo Kang
    Energy-efficient skewed static logic design with dual Vt. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:882-885 [Conf]
  961. Rui Wang, Kaushik Roy, Cheng-Kok Koh
    Short-circuit power analysis of an inverter driving an RLC load. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:886-889 [Conf]
  962. A. N. L. Chan, Chun Bing Guo, H. C. Luong
    A 1-V 2.4-GHz CMOS LNA with source degeneration as image-rejection notch filter. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:890-893 [Conf]
  963. Kaoru Watanabe, Masakazu Sengoku, Hiroshi Tamura, Keisuke Nakano, Shoji Shinoda
    Graph problems in multi-hop networks. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:894-897 [Conf]
  964. K. Mase, R. Noto, Keisuke Nakano, Keisuke Karasawa, Masakazu Sengoku, Shoji Shinoda
    A circuit-connection-based multihop wireless infrastructure for local communities. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:898-901 [Conf]
  965. Jari Nikara, Jarmo Takala, David Akopian, Jukka Saarinen
    Pipeline architecture for DCT/IDCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:902-905 [Conf]
  966. Minyi Fu, Vassil S. Dimitrov, Graham A. Jullien
    An efficient technique for error-free algebraic-integer encoding for high performance implementation of the DCT and IDCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:906-909 [Conf]
  967. Chi-Wai Lee, Chiu-sing Choy, Jan Butas, Cheong-fat Chan
    A pipelined dataflow small micro-coded asynchronous processor and its application to DCT. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:910-913 [Conf]
  968. Tay-Jyi Lin, Chein-Wei Jen
    An efficient 2-D DWT architecture via resource cycling. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:914-917 [Conf]
  969. Hiroshi Kawaguchi, Gang Zhang, Seongsoo Lee, Takayasu Sakurai
    An LSI for VDD-hopping and MPEG4 system based on the chip. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:918-921 [Conf]
  970. Vasily G. Moshnyaga, H. Tsuji
    Cache energy reduction by dual voltage supply. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:922-925 [Conf]
  971. Ilion Yi-Liang Hsiao, Ding-Hao Wang, Chein-Wei Jen
    Power modeling and low-power design of content addressable memories. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:926-929 [Conf]
  972. T. Yamasaki, A. Suzuki, D. Kobayashi, T. Shibata
    A fast self-convergent flash-memory programming scheme for MV and analog data storage. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:930-933 [Conf]
  973. Alessandro De Gloria, Mauro Olivieri
    An application specific multi-port RAM cell circuit for register renaming units in high speed microprocessors. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:934-937 [Conf]
  974. Seung-Moon Yoo, Chulwoo Kim, Seong-Ook Jung, Kwang-Hyun Baek, Sung-Mo Kang
    New current-mode sense amplifiers for high density DRAM and PIM architectures. [Citation Graph (0, 0)][DBLP]
    ISCAS (4), 2001, pp:938-941 [Conf]
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