Conferences in DBLP
Kiyoo Itoh Low-voltage memories for power-aware systems. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence T. Clark , Neil Deutscher , Shay Demmons , Franco Ricci Standby power management for a 0.18µm microprocessor. [Citation Graph (0, 0)][DBLP ] Conf ] Hyunsik Im Physical insight into fractional power dependence of saturation current on gate voltage in advanced short channel MOSFETS (alpha-power law model). [Citation Graph (0, 0)][DBLP ] Conf ] Siva Narendra , Vivek De , Shekhar Borkar , Dimitri Antoniadis , Anantha Chandrakasan Full-chip sub-threshold leakage power prediction model for sub-0.18 µm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Koichi Nose , Takayasu Sakurai Power-conscious interconnect buffer optimization with improved modeling of driver MOSFET and Its implications to bulk and SOI CMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Vijay Raghunathan , Saurabh Ganeriwal , Curt Schurgers , Mani B. Srivastava E2 WFQ: an energy efficient fair scheduling policy for wireless systems.Citation Graph (0, 0)][DBLP ] Conf ] Rex Min , Anantha Chandrakasan A framework for energy-scalable communication in high-density wireless networks. [Citation Graph (0, 0)][DBLP ] Conf ] Eui-Young Chung , Giovanni De Micheli , Luca Benini Contents provider-assisted dynamic voltage scaling for low energy multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Navid Azizi , Andreas Moshovos , Farid N. Najm Low-leakage asymmetric-cell SRAM. [Citation Graph (0, 0)][DBLP ] Conf ] Zhigang Hu , Philo Juang , Phil Diodato , Stefanos Kaxiras , Kevin Skadron , Margaret Martonosi , Douglas W. Clark Managing leakage for transient data: decay and quasi-static 4T memory cells. [Citation Graph (0, 0)][DBLP ] Conf ] Nikola Nedovic , Marko Aleksic , Vojin G. Oklobdzija Conditional pre-charge techniques for power-efficient dual-edge clocking. [Citation Graph (0, 0)][DBLP ] Conf ] Fatih Hamzaoglu , Mircea R. Stan Circuit-level techniques to control gate leakage for sub-100nm CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Ashish Srivastava , Robert Bai , David Blaauw , Dennis Sylvester Modeling and analysis of leakage power considering within-die process variations. [Citation Graph (0, 0)][DBLP ] Conf ] Rusell E. Henning , Chaitali Chakrabarti Low-power approach for decoding convolutional codes with adaptive viterbi algorithm approximations. [Citation Graph (0, 0)][DBLP ] Conf ] Morteza Maleki , Karthik Dantu , Massoud Pedram Power-aware source routing protocol for mobile ad hoc networks. [Citation Graph (0, 0)][DBLP ] Conf ] Edgar G. Daylight , Sven Wuytack , Chantal Ykman-Couvreur , Francky Catthoor Analyzing energy friendly steady state phases of dynamic application execution in terms of sparse data structures. [Citation Graph (0, 0)][DBLP ] Conf ] Yan Zhang , John Lach , Kevin Skadron , Mircea R. Stan Odd/even bus invert with two-phase transfer for buses with coupling. [Citation Graph (0, 0)][DBLP ] Conf ] Sunghyun Lee , Kiyoung Choi , Sungjoo Yoo An intra-task dynamic voltage scaling method for SoC design with hierarchical FSM and synchronous dataflow model. [Citation Graph (0, 0)][DBLP ] Conf ] Takanori Okuma , Yun Cao , Masanori Muroyama , Hiroto Yasuura Reducing access energy of on-chip data memory considering active data bitwidth. [Citation Graph (0, 0)][DBLP ] Conf ] Joohee Kim , Conrad H. Ziesler , Marios C. Papaefthymiou Energy recovering static memory. [Citation Graph (0, 0)][DBLP ] Conf ] Victor V. Zyuban , Stephen V. Kosonocky Low power integrated scan-retention mechanism. [Citation Graph (0, 0)][DBLP ] Conf ] Sandeep Dhar , Dragan Maksimovic , Bruno Kranzen Closed-loop adaptive voltage scaling controller for standard-cell ASICs. [Citation Graph (0, 0)][DBLP ] Conf ] Amaury Nève , Denis Flandre , Helmut Schettler , Thomas Ludwig 0004 , Gerhard Hellner Design of a branch-based 64-bit carry-select adder in 0.18 µm partially depleted SOI CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Inseok Choi , Hojun Shim , Naehyuck Chang Low-power color TFT LCD display for hand-held embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Alberto Macii , Enrico Macii , Massimo Poncino Discharge current steering for battery lifetime optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Osman S. Unsal , Israel Koren , C. Mani Krishna Towards energy-aware software-based fault tolerance in real-time systems. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Zhang , Krste Asanovic Fine-grain CAM-tag cache resizing using miss tags. [Citation Graph (0, 0)][DBLP ] Conf ] Aristides Efthymiou , Jim D. Garside An adaptive serial-parallel CAM architecture for low-power cache blocks. [Citation Graph (0, 0)][DBLP ] Conf ] Vasily G. Moshnyaga , Koji Inoue , Mizuka Fukagawa Reducing energy consumption of video memory by bit-width compression. [Citation Graph (0, 0)][DBLP ] Conf ] Koji Inoue , Vasily G. Moshnyaga , Keikichi Murakami A history-based I-cache for low-energy multimedia applications. [Citation Graph (0, 0)][DBLP ] Conf ] Daler N. Rakhmatov , Sarma B. K. Vrudhula , Deborah A. Wallach Battery lifetime prediction for energy-aware computing. [Citation Graph (0, 0)][DBLP ] Conf ] Eren Kursun , Ankur Srivastava , Seda Ogrenci Memik , Majid Sarrafzadeh Early evaluation techniques for low power binding. [Citation Graph (0, 0)][DBLP ] Conf ] Victor V. Zyuban , Philip N. Strenski Unified methodology for resolving power-performance tradeoffs at the microarchitectural and circuit levels. [Citation Graph (0, 0)][DBLP ] Conf ] Mark S. Lundstrom Is nanoelectronics the future of microelectronics? [Citation Graph (0, 0)][DBLP ] Conf ] Tejas Karkhanis , James E. Smith , Pradip Bose Saving energy with just in time instruction delivery. [Citation Graph (0, 0)][DBLP ] Conf ] Alper Buyuktosunoglu , David H. Albonesi , Pradip Bose , Peter W. Cook , Stanley Schuster Tradeoffs in power-efficient issue queue design. [Citation Graph (0, 0)][DBLP ] Conf ] Yazdan Aghaghiri , Massoud Pedram , Farzan Fallah Reducing transitions on memory buses using sector-based encoding technique. [Citation Graph (0, 0)][DBLP ] Conf ] Michael C. Huang , Jose Renau , Josep Torrellas Energy-efficient hybrid wakeup logic. [Citation Graph (0, 0)][DBLP ] Conf ] Kimiyoshi Usami , Naoyuki Kawabe , Masayuki Koizumi , Katsuhiro Seta , Toshiyuki Furusawa Automated selective multi-threshold design for ultra-low standby applications. [Citation Graph (0, 0)][DBLP ] Conf ] Kyu-won Choi , Abhijit Chatterjee HA2 TSD: hierarchical time slack distribution for ultra-low power CMOS VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Afshin Abdollahi , Massoud Pedram , Farzan Fallah Runtime mechanisms for leakage current reduction in CMOS VLSI circuits1, 2 . [Citation Graph (0, 0)][DBLP ] Conf ] Vojin G. Oklobdzija , Jens Sparsø Future directions in clocking multi-ghz systems. [Citation Graph (0, 0)][DBLP ] Conf ] Ulrich Kremer Compilers for power and energy management. [Citation Graph (0, 0)][DBLP ] Conf ] Omid Oliaei Oversampled gain-boosting. [Citation Graph (0, 0)][DBLP ] Conf ] Simon C. Li , Jimmy C. Cha ±0.5V ±1.5V VHF CMOS LV/LP four-quadrant analog multiplier in modified bridged-triode scheme. [Citation Graph (0, 0)][DBLP ] Conf ] Jincheol Yoo , Daegyu Lee , Kyusun Choi , Jongsoo Kim A power and resolution adaptive flash analog-to-digital converter. [Citation Graph (0, 0)][DBLP ] Conf ] Carl De Ranter , Michiel Steyaert Design techniques for low power high bandwidth upconversion in CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Magnus Ekman , Per Stenström , Fredrik Dahlgren TLB and snoop energy-reduction using virtual caches in low-power chip-multiprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Ryo Fujioka , Kiyokazu Katayama , Ryotaro Kobayashi , Hideki Ando , Toshio Shimada A preactivating mechanism for a VT-CMOS cache using address prediction. [Citation Graph (0, 0)][DBLP ] Conf ] Chris H. Kim , Kaushik Roy Dynamic Vt SRAM: a leakage tolerant cache memory for low voltage microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Amirali Baniasadi , Andreas Moshovos Asymmetric-frequency clustering: a power-aware back-end for high-performance processors. [Citation Graph (0, 0)][DBLP ] Conf ] Takeshi Sakamoto , Takashi Yamada , Mamoru Mukuno , Yoshifumi Matsushita , Yasoo Harada , Hiroto Yasuura Power analysis techniques for SoC with improved wiring models. [Citation Graph (0, 0)][DBLP ] Conf ] Wael El-Essawy , David H. Albonesi , Balaram Sinharoy A microarchitectural-level step-power analysis tool. [Citation Graph (0, 0)][DBLP ] Conf ] Ashok K. Murugavel , N. Ranganathan Power estimation of sequential circuits using hierarchical colored hardware petri net modeling. [Citation Graph (0, 0)][DBLP ] Conf ] Kavel M. Büyüksahin , Farid N. Najm High-level area estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Yu-Lung Hsu , Sying-Jyan Wang Retiming-based logic synthesis for low-power. [Citation Graph (0, 0)][DBLP ] Conf ] Chunhong Chen , Changjun Kang , Majid Sarrafzadeh Activity-sensitive clock tree construction for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Tobias Noll , Heinrich Meyr Designing SoC's. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad M. Mansour , Naresh R. Shanbhag Low-power VLSI decoder architectures for LDPC codes. [Citation Graph (0, 0)][DBLP ] Conf ] David Garrett , Chris Nicol , Andrew J. Blanksby , Chris Howland A low power normalized-LMS decision feedback equalizer for a wireless packet modem. [Citation Graph (0, 0)][DBLP ] Conf ] Jongsun Park , Woopyo Jeong , Hunsoo Choo , Hamid Mahmoodi-Meimand , Yongtao Wang , Kaushik Roy High performance and low power FIR filter design based on sharing multiplication. [Citation Graph (0, 0)][DBLP ] Conf ] Shoji Goto , Takashi Yamada , Norihisa Takayama , Yoshifumi Matsushita , Yasoo Harada , Hiroto Yasuura A low-power digital matched filter for spread-spectrum systems. [Citation Graph (0, 0)][DBLP ] Conf ] Davide Bertozzi , Luca Benini , Bruno Riccò Parametric timing and power macromodels for high level simulation of low-swing interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] William C. Athas , Lynn Youngs , Andrew Reinhart Compact models for estimating microprocessor frequency and power. [Citation Graph (0, 0)][DBLP ] Conf ] Alberto García , Lukusa D. Kabulepa , Manfred Glesner Efficient estimation of signal transition activity in MAC architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Michael Eiermann , Walter Stechele Novel modeling techniques for RTL power estimation. [Citation Graph (0, 0)][DBLP ] Conf ] 