Conferences in DBLP
Ki Won Lee Low power requirements for future digital life style. [Citation Graph (0, 0)][DBLP ] Conf ] Tsugio Makimoto , Yoshio Sakai Evolution of low power electronics and its future applications. [Citation Graph (0, 0)][DBLP ] Conf ] Chris H. Kim , Jae-Joon Kim , Saibal Mukhopadhyay , Kaushik Roy A forward body-biased low-leakage SRAM cache: device and architecture considerations. [Citation Graph (0, 0)][DBLP ] Conf ] Lawrence T. Clark , Byungwoo Choi , Michael Wilkerson Reducing translation lookaside buffer active power. [Citation Graph (0, 0)][DBLP ] Conf ] Yen-Jen Chang , Chia-Lin Yang , Feipei Lai A power-aware SWDR cell for reducing cache write power. [Citation Graph (0, 0)][DBLP ] Conf ] Amit Agarwal , Kaushik Roy A noise tolerant cache design to reduce gate and sub-threshold leakage in the nanometer regime. [Citation Graph (0, 0)][DBLP ] Conf ] Suhwan Kim , Stephen V. Kosonocky , Daniel R. Knebel Understanding and minimizing ground bounce during mode transition of power gating structures. [Citation Graph (0, 0)][DBLP ] Conf ] Luca Benini , Angelo Galati , Alberto Macii , Enrico Macii , Massimo Poncino Energy-efficient data scrambling on memory-processor interfaces. [Citation Graph (0, 0)][DBLP ] Conf ] Nachiketh R. Potlapally , Srivaths Ravi , Anand Raghunathan , Niraj K. Jha Analyzing the energy consumption of security protocols. [Citation Graph (0, 0)][DBLP ] Conf ] Inseok Choi , Hyung Soo Kim , Heonshik Shin , Naehyuck Chang LPBP: low-power basis profile of the Java 2 Micro Edition. [Citation Graph (0, 0)][DBLP ] Conf ] Hyun Suk Kim , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Erik Brockmeyer , Francky Catthoor , Mary Jane Irwin Estimating influence of data layout optimizations on SDRAM energy consumption. [Citation Graph (0, 0)][DBLP ] Conf ] Ravishankar Rao , Sarma B. K. Vrudhula , Daler N. Rakhmatov Analysis of discharge techniques for multiple battery systems. [Citation Graph (0, 0)][DBLP ] Conf ] Conrad H. Ziesler , Joohee Kim , Visvesh S. Sathe , Marios C. Papaefthymiou A 225 MHz resonant clocked ASIC chip. [Citation Graph (0, 0)][DBLP ] Conf ] Matthew Cooke , Hamid Mahmoodi-Meimand , Kaushik Roy Energy recovery clocking scheme and flip-flops for ultra low-energy applications. [Citation Graph (0, 0)][DBLP ] Conf ] Juan Antonio Carballo , Jeffrey L. Burns , Seung-Moon Yoo , Ivan Vo , V. Robert Norman A semi-custom voltage-island technique and its application to high-speed serial links. [Citation Graph (0, 0)][DBLP ] Conf ] Kyu-won Choi , Abhijit Chatterjee UDSM (ultra-deep sub-micron)-aware post-layout power optimization for ultra low-power CMOS VLSI. [Citation Graph (0, 0)][DBLP ] Conf ] Haihua Su , Frank Liu , Anirudh Devgan , Emrah Acar , Sani R. Nassif Full chip leakage estimation considering power supply and temperature variations. [Citation Graph (0, 0)][DBLP ] Conf ] Rajeev R. Rao , Ashish Srivastava , David Blaauw , Dennis Sylvester Statistical estimation of leakage current considering inter- and intra-die process variation. [Citation Graph (0, 0)][DBLP ] Conf ] Xuning Chen , Li-Shiuan Peh Leakage power modeling and optimization in interconnection networks. [Citation Graph (0, 0)][DBLP ] Conf ] Emrah Acar , Anirudh Devgan , Rahul M. Rao , Ying Liu , Haihua Su , Sani R. Nassif , Jeffrey L. Burns Leakage and leakage sensitivity computation for combinational circuits. [Citation Graph (0, 0)][DBLP ] Conf ] Rahul M. Rao , Jeffrey L. Burns , Anirudh Devgan , Richard B. Brown Efficient techniques for gate leakage estimation. [Citation Graph (0, 0)][DBLP ] Conf ] Benton H. Calhoun , Frank Honoré , Anantha Chandrakasan Design methodology for fine-grained leakage control in MTCMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Hyo-Sig Won , Kyo-Sun Kim , Kwang-Ok Jeong , Ki-Tae Park , Kyu-Myung Choi , Jeong-Taek Kong An MTCMOS design methodology and its application to mobile computing. [Citation Graph (0, 0)][DBLP ] Conf ] Cassondra Neau , Kaushik Roy Optimal body bias selection for leakage improvement and process compensation over different technology generations. [Citation Graph (0, 0)][DBLP ] Conf ] Bhaskar Chatterjee , Manoj Sachdev , Steven Hsu , Ram Krishnamurthy , Shekhar Borkar Effectiveness and scaling trends of leakage control techniques for sub-130nm CMOS technologies. [Citation Graph (0, 0)][DBLP ] Conf ] Nikhil Jayakumar , Sunil P. Khatri An ASIC design methodology with predictably low leakage, using leakage-immune standard cells. [Citation Graph (0, 0)][DBLP ] Conf ] Deming Chen , Jason Cong , Yiping Fan Low-power high-level synthesis for FPGA architectures. [Citation Graph (0, 0)][DBLP ] Conf ] Feng Gao , John P. Hayes ILP-based optimization of sequential circuits for low power. [Citation Graph (0, 0)][DBLP ] Conf ] Ankur Srivastava Simultaneous Vt selection and assignment for leakage optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Davoodi , Ankur Srivastava Effective graph theoretic techniques for the generalized low power binding problem. [Citation Graph (0, 0)][DBLP ] Conf ] David Nguyen , Abhijit Davare , Michael Orshansky , David G. Chinnery , Brandon Thompson , Kurt Keutzer Minimization of dynamic and static power through joint assignment of threshold voltages and sizing optimization. [Citation Graph (0, 0)][DBLP ] Conf ] Fujio Ishihara , Farhana Sheikh , Borivoje Nikolic Level conversion for dual-supply systems. [Citation Graph (0, 0)][DBLP ] Conf ] Koushik K. Das , Rajiv V. Joshi , Ching-Te Chuang , Peter W. Cook , Richard B. Brown New optimal design strategies and analysis of ultra-low leakage circuits for nano-scale SOI technology. [Citation Graph (0, 0)][DBLP ] Conf ] Saibal Mukhopadhyay , Kaushik Roy Modeling and estimation of total leakage current in nano-scaled CMOS devices considering the effect of parameter variation. [Citation Graph (0, 0)][DBLP ] Conf ] Kwang-Il Oh , Lee-Sup Kim A clock delayed sleep mode domino logic for wide dynamic OR gate. [Citation Graph (0, 0)][DBLP ] Conf ] Keunwoo Kim , Rajiv V. Joshi , Ching-Te Chuang Strained-si devices and circuits for low-power applications. [Citation Graph (0, 0)][DBLP ] Conf ] Qadeer Ahmad Khan , Sanjay Kumar Wadhwa , Kulbhushan Misri Low power startup circuits for voltage and current reference with zero steady state current. [Citation Graph (0, 0)][DBLP ] Conf ] Woo Young Choi , Jong Duk Lee , Byung-Gook Park Reverse-order source/drain formation with double offset spacer (RODOS) for CMOS low-power, high-speed and low-noise amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] Masayuki Miyazaki , Hidetoshi Tanaka , Goichi Ono , Tomohiro Nagano , Norio Ohkubo , Takayuki Kawahara , Kazuo Yano Electric-energy generation using variable-capacitive resonator for power-free LSI: efficiency analysis and fundamental experiment. [Citation Graph (0, 0)][DBLP ] Conf ] Stephen Tang , Siva Narendra , Vivek De Temperature and process invariant MOS-based reference current generation circuits for sub-1V operation. [Citation Graph (0, 0)][DBLP ] Conf ] Sung-Mo Kang Elements of low power design for integrated systems. [Citation Graph (0, 0)][DBLP ] Conf ] Weiping Liao , Fei Li , Lei He Microarchitecture level power and thermal simulation considering temperature dependent leakage model. [Citation Graph (0, 0)][DBLP ] Conf ] Seongmoo Heo , Kenneth Barr , Krste Asanovic Reducing power density through activity migration. [Citation Graph (0, 0)][DBLP ] Conf ] Michael D. Powell , T. N. Vijaykumar Pipeline muffling and a priori current ramping: architectural techniques to reduce high-frequency inductive noise. [Citation Graph (0, 0)][DBLP ] Conf ] Yiran Chen , Kaushik Roy , Cheng-Kok Koh Integrated architectural/physical planning approach for minimization of current surge in high performance clock-gated microprocessors. [Citation Graph (0, 0)][DBLP ] Conf ] Gurhan Kucuk , Dmitry Ponomarev , Oguz Ergin , Kanad Ghose Reducing reorder buffer complexity through selective operand caching. [Citation Graph (0, 0)][DBLP ] Conf ] Tao Li , Lizy Kurian John Routine based OS-aware microprocessor resource adaptation for run-time operating system power saving. [Citation Graph (0, 0)][DBLP ] Conf ] Werner Weber Ambient intelligence: industrial research on a visionary concept. [Citation Graph (0, 0)][DBLP ] Conf ] Dan Nicolaescu , Alexander V. Veidenbaum , Alexandru Nicolau Reducing data cache energy consumption via cached load/store queue. [Citation Graph (0, 0)][DBLP ] Conf ] Soontae Kim , Narayanan Vijaykrishnan , Mary Jane Irwin , Lizy Kurian John On load latency in low-power caches. [Citation Graph (0, 0)][DBLP ] Conf ] Gokhan Memik , Glenn Reinman , William H. Mangione-Smith Reducing energy and delay using efficient victim caches. [Citation Graph (0, 0)][DBLP ] Conf ] Youtao Zhang , Jun Yang Low cost instruction cache designs for tag comparison elimination. [Citation Graph (0, 0)][DBLP ] Conf ] Jun Yang , Youtao Zhang Lightweight set buffer: low power data cache for multimedia application. [Citation Graph (0, 0)][DBLP ] Conf ] Carlos Molina , Carles Aliagas , Montse Garcia , Antonio González , Jordi Tubella Non redundant data cache. [Citation Graph (0, 0)][DBLP ] Conf ] Emil Talpes , Diana Marculescu A critical analysis of application-adaptive multiple clock processors. [Citation Graph (0, 0)][DBLP ] Conf ] Karthik Natarajan , Heather Hanson , Stephen W. Keckler , Charles R. Moore , Doug Burger Microprocessor pipeline energy analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Pai H. Chou , Chulsung Park , Jae Park , Kien Pham , Jinfeng Liu B#: a battery emulator and power profiling instrument. [Citation Graph (0, 0)][DBLP ] Conf ] Kavel M. Büyüksahin , Priyadarsan Patra , Farid N. Najm ESTIMA: an architectural-level power estimator for multi-ported pipelined register files. [Citation Graph (0, 0)][DBLP ] Conf ] Amitabh Menon , S. K. Nandy , Mahesh Mehendale Multivoltage scheduling with voltage-partitioned variable storage. [Citation Graph (0, 0)][DBLP ] Conf ] Azadeh Davoodi , Ankur Srivastava Voltage scheduling under unpredictabilities: a risk management paradigm. [Citation Graph (0, 0)][DBLP ] Conf ] Hsien-Hsin S. Lee , Chinnakrishnan S. Ballapuram Energy efficient D-TLB and data cache using semantic-aware multilateral partitioning. [Citation Graph (0, 0)][DBLP ] Conf ] Jung-Hoon Lee , Gi-Ho Park , Sung-Bae Park , Shin-Dug Kim A selective filter-bank TLB system. [Citation Graph (0, 0)][DBLP ] Conf ] Andreas Moshovos Checkpointing alternatives for high performance, power-aware processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jude A. Rivers , Sameh W. Asaad , John-David Wellman , Jaime H. Moreno Reducing instruction fetch energy with backwards branch control information and buffering. [Citation Graph (0, 0)][DBLP ] Conf ] Hajime Shimada , Hideki Ando , Toshio Shimada Pipeline stage unification: a low-energy consumption technique for future mobile processors. [Citation Graph (0, 0)][DBLP ] Conf ] Jong-eun Lee , Kiyoung Choi , Nikil D. Dutt Energy-efficient instruction set synthesis for application-specific processors. [Citation Graph (0, 0)][DBLP ] Conf ] Reza Lotfi , Mohammad Taherzadeh-Sani , M. Yaser Azizi , Omid Shoaei A low-power design methodology for high-resolution pipelined analog-to-digital converters. [Citation Graph (0, 0)][DBLP ] Conf ] Hesam Amir Aslanzadeh , Saeid Mehrmanesh , M. B. Vahidfar , Amin Quasem Safarian , Reza Lotfi A 1-V 1-mW high-speed class AB operational amplifier for high-speed low power pipelined A/D converters using "Slew Boost" technique. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad Yavari , Omid Shoaei Low-voltage low-power fast-settling CMOS operational transconductance amplifiers for switched-capacitor applications. [Citation Graph (0, 0)][DBLP ] Conf ] Quoc-Hoang Duong , Trung-Kien Nguyen , Sang-Gug Lee Low-voltage low-power high dB-linear CMOS exponential function generator using highly-linear V-I converter. [Citation Graph (0, 0)][DBLP ] Conf ] Mohammad M. Ahmadi , Reza Lotfi A new architecture for rail-to-rail input constant-gm CMOS operational transconductance amplifiers. [Citation Graph (0, 0)][DBLP ] Conf ] James R. Heath A systems approach to molecular electronics. [Citation Graph (0, 0)][DBLP ] Conf ] Alice Wang , Anantha Chandrakasan Energy-aware architectures for a real-valued FFT implementation. [Citation Graph (0, 0)][DBLP ] Conf ] Seok-Jun Lee , Naresh R. Shanbhag , Andrew C. Singer A low-power VLSI architecture for turbo decoding. [Citation Graph (0, 0)][DBLP ] Conf ] Venkata Syam P. Rapaka , Diana Marculescu A mixed-clock issue queue design for globally asynchronous, locally synchronous processor cores. [Citation Graph (0, 0)][DBLP ] Conf ] Dmitry Ponomarev , Gurhan Kucuk , Oguz Ergin , Kanad Ghose Power efficient comparators for long arguments in superscalar processors. [Citation Graph (0, 0)][DBLP ] Conf ] Nam Sung Kim , Trevor N. Mudge The microarchitecture of a low power register file. [Citation Graph (0, 0)][DBLP ] Conf ] Daniel Chaver , Luis Piñuel , Manuel Prieto , Francisco Tirado , Michael C. Huang Branch prediction on demand: an energy-efficient solution. [Citation Graph (0, 0)][DBLP ] Conf ] Woonseok Kim , Jihong Kim , Sang Lyul Min Dynamic voltage scaling algorithm for fixed-priority real-time systems using work-demand analysis. [Citation Graph (0, 0)][DBLP ] Conf ] Jie S. Hu , A. Nadgir , Narayanan Vijaykrishnan , Mary Jane Irwin , Mahmut T. Kandemir Exploiting program hotspots and code sequentiality for instruction cache leakage management. [Citation Graph (0, 0)][DBLP ] Conf ] Dongkun Shin , Jihong Kim Power-aware scheduling of conditional task graphs in real-time multiprocessor systems. [Citation Graph (0, 0)][DBLP ] Conf ] Madhavi Gopal Valluri , Lizy Kurian John , Heather Hanson Exploiting compiler-generated schedules for energy savings in high-performance processors. [Citation Graph (0, 0)][DBLP ] Conf ] Hyung Gyu Lee , Naehyuck Chang Energy-aware memory allocation in heterogeneous non-volatile memory systems. [Citation Graph (0, 0)][DBLP ] Conf ] Jason Sungtae Kim , Michael Bedford Taylor , Jason E. Miller , David Wentzlaff Energy characterization of a tiled architecture processor with on-chip networks. [Citation Graph (0, 0)][DBLP ] Conf ] Domine Leenaerts Low power RF IC design for wireless communication. [Citation Graph (0, 0)][DBLP ] Conf ] Jonghae Kim , Jean-Olivier Plouchart , Noah Zamdmer , Melanie Sherony , Yue Tan , Meeyoung Yoon , Robert Trzcinski , Mohamed Talbi , John Safran , Asit Ray , Lawrence F. Wagner A power-optimized widely-tunable 5-GHz monolithic VCO in a digital SOI CMOS technology on high resistivity substrate. [Citation Graph (0, 0)][DBLP ] Conf ] Jean-Olivier Plouchart , Jonghae Kim , Hector Recoules , Noah Zamdmer , Yue Tan , Melanie Sherony , Asit Ray , Lawrence F. Wagner A 0.123 mW 7.25 GHz static frequency divider by 8 in a 120-nm SOI technology. [Citation Graph (0, 0)][DBLP ] Conf ] Chih-Jen Yen , Mely Chen Chi , Wen-Yaw Chung , Shing-Hao Lee A 0.75-mW analog processor IC for wireless biosignal monitor. [Citation Graph (0, 0)][DBLP ] Conf ] Drew Guckenberger , Kevin T. Kornegay Integrated DC-DC converter design for improved WCDMA power amplifier efficiency in SiGe BiCMOS technology. [Citation Graph (0, 0)][DBLP ] Conf ] Payam Heydari , Ying Zhang A novel high frequency, high-efficiency, differential class-E power amplifier in 0.18mum CMOS. [Citation Graph (0, 0)][DBLP ] Conf ] Eun Jung Kim , Ki Hwan Yum , Greg M. Link , Narayanan Vijaykrishnan , Mahmut T. Kandemir , Mary Jane Irwin , Mazin S. Yousif , Chita R. Das Energy optimization techniques in cluster interconnects. [Citation Graph (0, 0)][DBLP ] Conf ] Flavius Gruian , Krzysztof Kuchcinski Uncertainty-based scheduling: energy-efficient ordering for tasks with variable execution time. [Citation Graph (0, 0)][DBLP ] Conf ] Sung I. Park , Vijay Raghunathan , Mani B. Srivastava Energy efficiency and fairness tradeoffs in multi-resource, multi-tasking embedded systems. [Citation Graph (0, 0)][DBLP ] Conf ] Farinaz Koushanfar , Abhijit Davare , Dai Tho Nguyen , Miodrag Potkonjak , Alberto L. Sangiovanni-Vincentelli Low power coordination in wireless ad-hoc networks. [Citation Graph (0, 0)][DBLP ] Conf ] Aman Kansal , Mani B. Srivastava An environmental energy harvesting framework for sensor networks. [Citation Graph (0, 0)][DBLP ] Conf ] 